Synopsys Inc logo

Synopsys Inc

Synopsys Inc

Our Technology. Your Innovation.

๐Ÿ“ Sunnyvale, California

25 Open Positions
9 Active Locations
Posted
Top Employer

About Synopsys Inc

Synopsys Inc develops electronic design automation (EDA) software and semiconductor intellectual property (IP) products from its headquarters in Mountain View, California. Its tools support the design of complex integrated circuits and systems-on-chip, with notable products including Design Compiler and PrimeTime, which are widely used in the semiconductor industry. Engineering disciplines at Synopsys include digital and analog design, verification, and physical design. Engineers solve challenges related to power, performance, and area optimization in chip design. With a workforce of approximately 15,000 employees, Synopsys operates globally, providing a comprehensive suite of tools that streamline the design process for leading semiconductor companies.

Current Job Openings

25 jobs

All Synopsys Inc Job Openings

  • Synopsys Inc logo

    Analog Design, Sr Staff Engineer - 18144

    @ Synopsys Inc

    ๐Ÿ“Kanata, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    op-amps SERDES DDR
    View Analog Design, Sr Staff Engineer - 18144
  • Synopsys Inc logo

    Staff Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    IBIS DDR LPDDR
    View Staff Analog Design Engineer
  • Synopsys Inc logo

    Analog Design, Sr Staff Engineer - 17998

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes MATLAB DSP
    View Analog Design, Sr Staff Engineer - 17998
  • Synopsys Inc logo

    ASIC Digital Design, Staff Engineer -18138

    @ Synopsys Inc

    ๐Ÿ“Boxborough, MA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Verilog Perl
    View ASIC Digital Design, Staff Engineer -18138
  • Synopsys Inc logo

    ASIC Physical Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL-to-GDSII UCIe HBM
    View ASIC Physical Design, Engineer
  • Synopsys Inc logo

    Analog Design - Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes PLLs CDR
    View Analog Design - Staff Engineer
  • Synopsys Inc logo

    ASIC Digital Verification, Sr Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Eindhoven, North Brabant, Netherlands, Netherlands ๐Ÿ‡ณ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM verification
    View ASIC Digital Verification, Sr Staff Engineer
  • Synopsys Inc logo

    ASIC Physical Design Apprenticeship

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    VLSI Tcl Perl
    View ASIC Physical Design Apprenticeship
  • Synopsys Inc logo

    FPGA Prototyping Applications Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA VHDL Verilog
    View FPGA Prototyping Applications Engineer
  • Synopsys Inc logo

    Senior Application Engineer - FPGA/Prototyping

    @ Synopsys Inc

    ๐Ÿ“Raanana, Center District, Israel, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA SystemVerilog UNIX
    View Senior Application Engineer - FPGA/Prototyping
  • Synopsys Inc logo

    FPGA Prototyping/ Emulation Staff Application Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog Synthesis
    View FPGA Prototyping/ Emulation Staff Application Engineer
  • Synopsys Inc logo

    Architect - FPGA Design, AXI/ UCIe Protocol

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA PCIe CXL
    View Architect - FPGA Design, AXI/ UCIe Protocol
  • Synopsys Inc logo

    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC GDSII PrimeTime
    View ASIC Physical Design, Staff Engineer
  • Synopsys Inc logo

    Analog Design, Sr.Staff Engineer-15024

    @ Synopsys Inc

    ๐Ÿ“Boxborough, MA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes CMOS FinFET
    View Analog Design, Sr.Staff Engineer-15024
  • Synopsys Inc logo

    ASIC Design Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verification SystemVerilog UVM
    View ASIC Design Verification Engineer
  • Synopsys Inc logo

    FPGA Prototyping Staff Applications Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog SystemVerilog
    View FPGA Prototyping Staff Applications Engineer
  • Synopsys Inc logo

    Senior Staff Analog Design Engineer- 16906

    @ Synopsys Inc

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    transceiver UCIe SerDes
    View Senior Staff Analog Design Engineer- 16906
  • Synopsys Inc logo

    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, County Dublin, Ireland, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL PCIe DDR
    View ASIC Digital Design, Sr Staff Engineer
  • Synopsys Inc logo

    ASIC Digital Design/Verification Manager hot job

    @ Synopsys Inc

    ๐Ÿ“Hsinchu City, Taiwan, Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
    View ASIC Digital Design/Verification Manager
  • Synopsys Inc logo

    Staff Hardware Engineer

    @ Synopsys Inc

    ๐Ÿ“La Jolla Amago, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SolidWorks Creo Teamcenter
    View Staff Hardware Engineer
  • Synopsys Inc logo

    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog DFT
    View ASIC Digital Design, Sr Staff Engineer
  • Synopsys Inc logo

    ASIC Digital Design Intern

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL Verilog Perl
    View ASIC Digital Design Intern
  • Synopsys Inc logo

    Firmware Development Engineer

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C DDR LPDDR
    View Firmware Development Engineer
  • Synopsys Inc logo

    ASIC Digital Design Senior Manager

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog STA
    View ASIC Digital Design Senior Manager
  • Synopsys Inc logo

    Scientist- ASIC Verification, Interface IP- PCIe/CXL hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification UVM PCIe
    View Scientist- ASIC Verification, Interface IP- PCIe/CXL
  • Previously posted positions that may provide insight into Synopsys Inc's hiring patterns

  • Expired
    Synopsys Inc logo

    Staff Engineer Analog Design- Serdes

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes PLLs SPICE
    View details
    View Staff Engineer Analog Design- Serdes
  • Expired
    Synopsys Inc logo

    R&D Engineering, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL EDA Verilog
    View details
    View R&D Engineering, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Sr Manager

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UVM
    View details
    View ASIC Digital Design, Sr Manager
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog DDR
    View details
    View ASIC Digital Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog DDR
    View details
    View ASIC Digital Design, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SPICE SerDes equalizers
    View details
    View Analog Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    PCB Layout Engineer, Sr Staff

    @ Synopsys Inc

    ๐Ÿ“Taipei, Taipei City, Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCB EDA Allegro
    View details
    View PCB Layout Engineer, Sr Staff
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Sr Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UCIe
    View details
    View ASIC Digital Design, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UCIe
    View details
    View ASIC Digital Design, Principal Engineer
  • Expired
    Synopsys Inc logo

    Senior Staff RTL Design Engineers

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog TCL
    View details
    View Senior Staff RTL Design Engineers
  • Expired
    Synopsys Inc logo

    Senior RTL Design & Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View Senior RTL Design & Verification Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Architect

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog SERDES DDR
    View details
    View Analog Design, Architect
  • Expired
    Synopsys Inc logo

    Lab Analog Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Lisbon, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal debugging
    View details
    View Lab Analog Design, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    FPGA Prototyping Applications Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog VHDL
    View details
    View FPGA Prototyping Applications Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    transistors PLLs VCOs
    View details
    View Analog Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    Senior Analog Design Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, Telangana, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FinFET SERDES CMOS
    View details
    View Senior Analog Design Engineer
  • Expired
    Synopsys Inc logo

    IP Design Technical Lead/ Staff ASIC RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Verilog
    View details
    View IP Design Technical Lead/ Staff ASIC RTL Design Engineer
  • Expired
    Synopsys Inc logo

    Senior Staff RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View Senior Staff RTL Design Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Austin, TX, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SystemVerilog UVM PCIe
    View details
    View ASIC Digital Verification, Principal Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Austin, TX, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC RTL EDA
    View details
    View ASIC Digital Design, Principal Engineer
  • Expired
    Synopsys Inc logo

    Staff ASIC Design Verification Engineer-17716

    @ Synopsys Inc

    ๐Ÿ“Nepean, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC System Verilog UVM
    View details
    View Staff ASIC Design Verification Engineer-17716
  • Expired
    Synopsys Inc logo

    RF Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Lisbon, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal CMOS
    View details
    View RF Analog Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Physical Design Apprenticeship

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    VLSI Tcl Python
    View details
    View ASIC Physical Design Apprenticeship
  • Expired
    Synopsys Inc logo

    ASIC Physical Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    physical design automation
    View details
    View ASIC Physical Design, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SoC Tcl
    View details
    View ASIC Physical Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog ASIC
    View details
    View ASIC Digital Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    FPGA IP Prototyping

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog Tcl
    View details
    View FPGA IP Prototyping
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Manager-IP Verification

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM VMM OVM
    View details
    View ASIC Digital Design, Manager-IP Verification
  • Expired
    Synopsys Inc logo

    ASIC Verification Engineer, Sr Staff

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC verification VCS
    View details
    View ASIC Verification Engineer, Sr Staff
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View ASIC Digital Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    R&D Engineer - PhD on Safety of AI/ML-based Embedded Systems for Autonomy

    @ Synopsys Inc

    ๐Ÿ“Montigny-le-Bretonneux, รŽle-de-France, France, France ๐Ÿ‡ซ๐Ÿ‡ท
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    machine learning safety
    View details
    View R&D Engineer - PhD on Safety of AI/ML-based Embedded Systems for Autonomy
  • Expired
    Synopsys Inc logo

    ASIC Verification, Senior Staff Engineer - 13121

    @ Synopsys Inc

    ๐Ÿ“Nepean, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
    View ASIC Verification, Senior Staff Engineer - 13121
  • Expired
    Synopsys Inc logo

    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS SPICE Python
    View details
    View Analog Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    Sr. Staff R&D Engineer, Analog design-17614

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI Python EDA
    View details
    View Sr. Staff R&D Engineer, Analog design-17614
  • Expired
    Synopsys Inc logo

    Sr. Manager, ASIC Verification - Interface IP- PCIe/CXL hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCIe CXL UVM
    View details
    View Sr. Manager, ASIC Verification - Interface IP- PCIe/CXL
  • Expired
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Porto, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog MATLAB
    View details
    View ASIC Digital Design, Sr Staff Engineer
  • Expired
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    Principal ASIC Implementation Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC Tcl Perl
    View details
    View Principal ASIC Implementation Engineer
  • Expired
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    Senior Staff RTL Design Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Ethernet Verilog
    View details
    View Senior Staff RTL Design Engineer
  • Expired
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog SerDes Hspice
    View details
    View Analog Design, Staff Engineer
  • Expired
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    Project Engineering Management

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    semiconductor project scheduling
    View details
    View Project Engineering Management
  • Expired
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    RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL DFT JTAG
    View details
    View RTL Design Engineer
  • Expired
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    Architect - FPGA Design, AXI/ UCIe Protocol

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA PCIe CXL
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    Sr. Staff Application Engineer, FPGA Prototyping-17205

    @ Synopsys Inc

    ๐Ÿ“Austin, TX, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA validation debug
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    ASIC Physical Design, Sr Staff Engineer in HCMC or Da Nang

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GDSII RTL STA
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    SoC Design Manager hot job

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    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC Fusion ICC2
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    ASIC Verification- Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Perl
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    Architect- FPGA Design, PCIe Protocol hot job

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA PCIe CXL
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    Memory Compiler Design โ€“ Sr. Architect

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    memory compiler Hspice
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    R&D Engineering, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C# WPF Tcl
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    Analog Design, Sr Staff Engineer - 17402

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes PAM4 FinFET
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS DDR HBM
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    Analog Design, Staff Engineer

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    ๐Ÿ“Hyderabad, Telangana, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES PAM4 NRZ
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    Analog Design, Sr Manager

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog circuit mixed-signal
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS DDR HBM
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    Senior Analog Design Engineer

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    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PLL EDA Python
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    ASIC Digital Design, Sr Manager - IP Verification- PCIe/CXL

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCIe CXL UVM
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    Senior RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog FPGA
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    Senior/Lead Asic Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog Verilog UVM
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    ASIC Digital Design, Staff Engineer - 17509

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C/C++ Jenkins Python
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    ASIC digital Design, Architect

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog PCIe
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    ASIC Digital Design Engineer-17369

    @ Synopsys Inc

    ๐Ÿ“Boxborough, MA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog TCL Python
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    Lead RTL Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM EDA
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    ASIC Digital Design, Architect

    @ Synopsys Inc

    ๐Ÿ“Dublin, County Dublin, Ireland, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC DDR PCIe
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC UVM SystemVerilog
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    ASIC Digital Design, Sr Manager hot job

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    USB RTL PCIe
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Gdansk Metropolitan Area, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS SerDes Drivers
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    Analog Design, Principal Engineer - 17007

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SerDes CMOS SPICE
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    ASIC Physical Design Senior Manager

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC VLSI RTL
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    Analog Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES CMOS Verilog-A
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    ASIC Physical Design Senior Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC GDSII PrimeTime
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    ASIC Physical Design, Staff Engineer in Da Nang

    @ Synopsys Inc

    ๐Ÿ“ฤร  Nang, Da Nang City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC GDSII UCIe
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    ASIC Digital Design Verification, Principal Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Munich, Bavaria, Germany, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SystemVerilog UVM SVA
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    ASIC Implementation Project Engineering Management, Sr Staff hot job

    @ Synopsys Inc

    ๐Ÿ“Hsinchu City, Taiwan, Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SoC FinFET
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL GDSII PnR
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    RF Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Porto, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog SerDes CMOS
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    Technical Product Management, Sr Staff

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC MRAM TCAM
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    Lab Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Lisbon, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal debugging
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    Analog Design, Engineer - 16712

    @ Synopsys Inc

    ๐Ÿ“Markham, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog mixed-signal Python
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    FPGA Prototyping Applications Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA TCL Python
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    Hardware Engineer

    @ Synopsys Inc

    ๐Ÿ“Rungis, รŽle-de-France, France, France ๐Ÿ‡ซ๐Ÿ‡ท
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CAD PCB simulation
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    Embedded Memory Circuit Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    memory CMOS circuit
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, Telangana, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ICC2 FinFet DC
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    ASIC Digital Verification Staff Engineer in HCMC/ Da Nang / Hanoi

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC VCS UVM
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    Senior Software Engineer - Device Driver and Firmware

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C/C++ Linux Python
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    Principal ASIC Design Verification Engineer-16988 hot job

    @ Synopsys Inc

    ๐Ÿ“Nepean, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
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    UCIe Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Analog IC CMOS
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    FPGA Applications Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA Verilog SystemVerilog
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DDR HBM IP
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    Analog Design Senior Architect - 14565

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes EDA IC
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    R&D Engineer, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Verilog VHDL
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    Solutions Engineering, Sr Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL DFT JTAG
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    PCB Layout Engineer, Staff hot job

    @ Synopsys Inc

    ๐Ÿ“Taipei, Taipei City, Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCB EDA Altium
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    SoC Design and Verification Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    EDA Verilog SystemVerilog
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    ASIC Digital Verification Engineer, Staff hot job

    @ Synopsys Inc

    ๐Ÿ“Moreira, Porto, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC HBM DDR
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    Principal RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    R&D Engineering, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SoC emulation verification
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    Analog Design, Staff Engineer - 17085

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes PAM4 CMOS
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT ATPG Spyglass
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    Staff R&D Software Engineer โ€“ RTL Restructuring & Transformation

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ RTL Verilog
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    ASIC Digital Design, Sr Manager

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCIe RTL CXL
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    R&D Engineering, Sr Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog EDA
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    RF Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Lisbon, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog mixed-signal CMOS
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    Lead RTL Design Engineer, IP Development hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog PCIe
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC DDR STA
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    Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Wuhan, Hubei, China, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SerDes SPICE Verilog-A
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    ASIC Digital Design Architect

    @ Synopsys Inc

    ๐Ÿ“Dublin, County Dublin, Ireland, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL DDR
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    RTL Design & Verification - Senior Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    SoC Firmware-Hardware Validation Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Lisbon, Portugal, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    silicon validation Python
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    ASIC Physical Design, Sr Staff Engineer

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    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    ASIC physical scripting
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    Analog Design, Staff Engineer

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    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    SPICE Spectre PLLs
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    R&D Engineering, Staff Engineer

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    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    C++ Verilog VHDL
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    Staff RTL Design Engineer

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    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    RTL Verilog SERDES
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    ASIC Digital Design Architect

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    ๐Ÿ“Austin, TX, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    ASIC DDR PCIe
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    ASIC Digital Design, Sr Staff Engineer - Processor RTL Design

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    ๐Ÿ“Hyderabad, Telangana, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC RISC Verilog
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    R&D Engineering, Staff Engineer

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    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    C++ CUDA GPU
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    Analog Design, Sr Supervisor

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    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    analog SPICE STA
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    Senior Staff R&D Engineering - 16038

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    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    analog compiler Python
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    Firmware Development Engineer

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    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    C Perl TCL
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    ASIC Digital, Verification Engineer - Senior Staff -14704 hot job

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    ๐Ÿ“Nepean, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    IP DDR SerDes
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    ASIC Digital Design, RTL - 16908

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    ๐Ÿ“Boxborough, MA, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SerDes DDR HBM
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    Memory Compiler Architect - 15954

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    memory Python Hspice
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    Staff ASIC Project Engineering Manager-16504

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    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC IC SerDes
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    ASIC Digital Design, Sr Staff Engineer - Verification

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    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    VCS UVM UPF
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    Analog Design, Architect โ€“ Highโ€‘Speed SerDes - 14576

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    ๐Ÿ“Markham, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
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    SerDes PLL TX
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    ASIC Digital Design Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Reading, England, United Kingdom, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
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    System Verilog UVM SVA
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    Senior System Architect, Analog Design-13383

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    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SERDES modelling equalization
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    Quantum Algorithms Development Internship

    @ Synopsys Inc

    ๐Ÿ“Canonsburg, PA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š internship
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    quantum algorithms linear
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    RTL Design & Verification Engineer

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    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
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    RTL Verilog SystemVerilog
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    ASIC Digital Design Sr Staff Engineer - Verification

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    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    SystemVerilog UVM Perl
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    ASIC Physical Design, Sr Director in HCMC/ Da Nang

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    physical design interconnect
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    Applications Engineering, Staff Engineer - RF/PCB/Circuits

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    ๐Ÿ“Austin, TX, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    Ansys HFSS SIwave
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    High-Speed Interface Analog Design Engineer, Staff

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    ๐Ÿ“Gdansk Metropolitan Area, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
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    CMOS SERDES UNIX
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    ASIC Digital Design, Principal Engineer hot job

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    ๐Ÿ“Dublin, County Dublin, Ireland, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
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    ASIC RTL EDA
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    ASIC Design/Verification, Architect

    @ Synopsys Inc

    ๐Ÿ“Reading, England, United Kingdom, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
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    ASIC System Verilog UVM
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    SoC Design Verification , Staff

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog UVM AXI
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    ASIC Physical Design Intern

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š intern
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    ASIC GDSII CMOS
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    ASIC Digital Design, Manager hot job

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    ๐Ÿ“Ottawa, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Verilog VHDL
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    Applications Engineering, Sr Staff Engineer- RTL-to-GDS/Fusion Compiler

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    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL GDS EDA
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    Lead RTL Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š lead
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    SystemVerilog UVM HDL
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    Senior Product Sales Manager

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    ๐Ÿ“Novi, MI, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
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    sales communication networking
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    ASIC Digital Design, Principal- 15193

    @ Synopsys Inc

    ๐Ÿ“Nepean, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
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    ASIC UVM DDR
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    R&D Engineering, Architect- FPGA Design-PCIe Protocol

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    ๐Ÿ“Sunnyvale, CA, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA CXL PCIe
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    Senior ASIC Digital Designer - 15194

    @ Synopsys Inc

    ๐Ÿ“Nepean, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC UVM Python
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    R&D Engineering, Sr Staff Engineer

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    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    RTL Verilog SystemVerilog
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    ASIC Physical Design, Principal Engineer in Tan Binh district

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    ๐Ÿ“Ho Chi Minh City, Ho Chi Minh City, Vietnam, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    RTL GDSII PnR
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    ASIC Digital IP Design/Verification, Architect

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    ๐Ÿ“Reading, England, United Kingdom, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL HBM
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    ASIC Digital Design, Architect

    @ Synopsys Inc

    ๐Ÿ“Dublin, County Dublin, Ireland, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
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    โฑ๏ธŽ full-time
    ASIC HBM PCIe
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    Analog Design, Staff Engineer

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    ๐Ÿ“Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal SPICE
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    Staff Analog Design Engineer

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    ๐Ÿ“Hyderabad, Telangana, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog SERDES FinFET
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    Firmware Engineer, Sr. Staff 17011

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    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C++ Python
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    Analog Design Architect

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    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ
    transceiver silicon photonics
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    Principal Engineer- ASIC Digital Design

    @ Synopsys Inc

    ๐Ÿ“Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC RTL Verilog
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    Principal ASIC Digital Verification Engineer- IP Development hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC UVM SystemVerilog
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    Sr/Staff AE for Physical Implementation RTL-GDS

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    implementation scripting PPA
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    ASIC Digital Design, Sr Staff/Principal Engineer - DDR

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL Verilog
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    ASIC Digital Design, Architect - 13370

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC PCIe Ethernet
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    RTL Design Staff Engineer in Ho Chi Minh city

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SystemVerilog Verilog
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS DDR ESD
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    Senior Staff Analog Design Enginee

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog CMOS FinFET
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    Embedded Systems Security Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    security vulnerabilities automation
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    ASIC Digital Design Engineer - 16702

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    C/C++ Python RTL
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    Analog Design Engineer

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    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog mixed-signal SerDes
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    ASIC Physical Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI DDR Tcl
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    Soc Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Synthesis LEC STA
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    Staff ASIC Digital Design Engineer - 15996

    @ Synopsys Inc

    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog PERL TCL
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    Digital Design Verification โ€“ Application Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Reading, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    Senior Staff R&D Engineer

    @ Synopsys Inc

    ๐Ÿ“Seongnam, South Korea ๐Ÿ‡ฐ๐Ÿ‡ท
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Gdansk Metropolitan Area, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS SERDES IC
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    Analog Design, Principal Engineer- 14131

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SerDes CMOS ADC
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    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCIe CXL UCIe
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    Digital Design Verification Engineer - 14915

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Verilog
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    ASIC Digital Design Verification Engineer - 16906

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM DDR
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    ASIC Digital Design, Principal Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Munich, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC RTL EDA
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    ASIC Digital Design, Sr Engineer - 16245

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC FPGA Verilog
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    SOC Engineering, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL2GDSII synthesis place
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    ASIC Verification- Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog UVM Perl
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog UVM DDR
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Brazil ๐Ÿ‡ง๐Ÿ‡ท
    ๐Ÿ“Š mid-level
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    CMOS SerDes Cadence
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    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog System Verilog UVM
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    ASIC Digital Design, Senior Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    RTL SystemVerilog Verilog
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    High-Speed Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SerDes CMOS FinFET
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    ASIC Digital Design, Sr. Engineer - 16592

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
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    SystemVerilog UVM Jira
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    ASIC Physical Design, Sr Staff Engineer - 16724

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC SoC STA
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    ASIC Physical Design, Staff Engineer -16723

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC SoC GDSII
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    Analog Design, Engineer - 16629

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
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    analog mixed-signal scripting
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Brazil ๐Ÿ‡ง๐Ÿ‡ท
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    CMOS ADC DAC
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    Analog Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
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    analog CMOS ADC
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    Analog Design, Staff Engineer - 16591

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    analog SERDES CMOS
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    Principal Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
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    analog SerDes MATLAB
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
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    CMOS ADC DAC
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    R&D Engineering, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    C++ SystemVerilog Verilog
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    Analog Layout Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    โฑ๏ธŽ full-time
    Cadence Synopsys Calibre
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    ASIC Physical Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC DDR EDA
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    ASIC Digital Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    PCIe UVM SystemVerilog
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    Senior Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SerDes CMOS FinFET
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
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    analog CMOS SerDes
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    Analog Layout Engineer, Staff

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    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
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    Cadence Synopsys Calibre
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    Lead RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    RTL Verilog SystemVerilog
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    Principal GPU simulation Software Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š lead
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    C++ Verilog SystemVerilog
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC verification UVM
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    ASIC Digital Design, Sr Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    UVM SystemVerilog testbenches
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    Sr Staff SoC Engineer

    @ Synopsys Inc

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
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    Floorplan Place DRC
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    Analog Design, Sr Staff Engineer - 13846 hot job

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    packaging EDA silicon
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    Principal Analog Design Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SerDes PLLs DLLs
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    SerDes FinFET ASIC
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    ASIC Digital Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SystemVerilog UVM PCIe
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    ASIC RTL PCIe
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    Analog Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    SERDES FinFET PAM4
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    ASIC/SoC Presales Applications Engineer - 16648

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    ASIC SoC PCIe
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    Senior/Staff ASIC Design Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC RTL UVM
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    Senior Staff Firmware Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    C++ Firmware SoC
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    ASIC Digital Design, Senior Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    ASIC RTL PCIe
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    Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    SERDES CMOS SPICE
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
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    analog CMOS SERDES
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    GPU R&D Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    CUDA C++ Python
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    Senior FPGA Engineer

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    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
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    FPGA Verilog PCIe
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    Application Engineer : Quantum ATK

    @ Synopsys Inc

    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    semiconductor EEC Python
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    Analog Design, Staff Engineer - SERDES

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    CMOS SPICE PCIe
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    ASIC Physical Design, Sr Staff

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    ASIC Synthesis Place&Route
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    RTL Design & Verification Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
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    RTL Verilog SystemVerilog
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    Analog Design Engineer โ€“ DDR I/O

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog CMOS DDR
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    RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    DFT BIST JTAG
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    ASIC Digital Design Engineer, Staff

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VCS Verdi UVM
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    Analog Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
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    SerDes CMOS EDA
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    SOC Engineering, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL2GDSII Synthesis PrimeTime
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    Analog Layout, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS FinFET GAA
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    ASIC Digital Design Engineer, Sr. Staff-15469

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C/C++ Jenkins
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    RTL/ Synthesis Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL synthesis VCS
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    IC SerDes Op-Amps
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    Sr Staff SoC Engineer

    @ Synopsys Inc

    ๐Ÿ“Beijing, China ๐Ÿ‡จ๐Ÿ‡ณ
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    Floorplan Place DRC/LVS
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    UCIe Analog Design Senoir Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog CMOS Cadence
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    Staff ASIC RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL Verilog
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    SOC Engineering, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
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    โฑ๏ธŽ full-time
    SOC RTL DFT
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    ASIC Digital Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    RTL Verilog Synthesis
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    ASIC Digital Design, Sr Staff/Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL Verilog
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    SOC Engineering, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SOC micro-architecture RTL
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    ASIC Digital Design, Staff Engineer - Verification

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    โฑ๏ธŽ full-time
    VCS UVM SVA
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    ASIC Digital Design, Sr Engineer - Verification

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    โฑ๏ธŽ full-time
    VCS Verdi UVM
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    Staff SOC Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    RTL2GDSII synthesis place
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    Senior/Staff - Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    โฑ๏ธŽ full-time
    analog CMOS SERDES
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FinFet FDSOI BCD
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    ASIC UVM SystemVerilog
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    SoC Firmware-Hardware Validation Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    silicon analog Python
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    Soc Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SOC Fusion Verification
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    ASIC Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Reading, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š principal
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    ASIC SystemVerilog UVM
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    Analog Design, Principal Engineer - 15244 hot job

    @ Synopsys Inc

    ๐Ÿ“Chandler, AZ, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    analog mixed-signal simulation
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    ASIC Digital Design, Architect

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL EDA
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    Soc Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SOC Fusion ICC2
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    Firmware Engineer, Sr. Engineer - 15393

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C/C++ SerDes
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC DDR HBM
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    Soc Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SOC LEC
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    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC HDL SERDES
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    ASIC Physical Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC VLSI DDR
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    Senior Staff SOC Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL2GDSII synthesis place
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    Senior Staff SOC Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL2GDSII synthesis timing
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    RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware SerDes digital
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    Staff Firmware Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware SerDes scripting
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    ASIC Digital Design, Principal Engineer - 14122

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
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    Senior ASIC Digital Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL Verilog
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    Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog CAD EDA
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    Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    analog CAD EDA
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    Senior Firmware Engineer

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C/C++ SerDes
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    Sr RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog AMBA Lint
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    Embedded Systems Software Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Python GDB
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification VCS Verdi
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    Staff Design Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    ASIC Security Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Eindhoven, Netherlands ๐Ÿ‡ณ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL SystemVerilog UVM
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    Analog Design, Sr Staff Engineer - 13584

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES CMOS Verilog-A
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    Analog Design, Sr. Engineer - 15254

    @ Synopsys Inc

    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS DDR SerDes
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    Staff Firmware Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C Perl TCL
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    Firmware Development Engineer, Senior Staff

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C DDR LPDDR
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    Sr. Firmware Design Engineer- 13993

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C Verilog
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    SOC Engineering, Director

    @ Synopsys Inc

    ๐Ÿ“Berlin, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC IP verification
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    Analog Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    PLL data converters SERDES
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog MATLAB
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    firmware SerDes scripting
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    Analog Layout Design, Sr Engineer in HCMC

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Cadence Synopsys Mentor
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    ASIC Physical Design, Principal Engineer-15046

    @ Synopsys Inc

    ๐Ÿ“Boxborough, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC DDR HBM
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Munich, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM SVA
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Reading, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC Fusion design
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    ASIC Digital Design, Architect

    @ Synopsys Inc

    ๐Ÿ“Reading, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Fusion Timing
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL EDA IP
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    ASIC Digital Design, Principal Engineer-14687

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    Verilog SerDes DFT
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    Principal Engineer, ASIC Digital Design

    @ Synopsys Inc

    ๐Ÿ“Munich, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC RTL EDA
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    ASIC Digital Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UVM
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC RTL EDA
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC VLSI DDR
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Reading, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC RTL EDA
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    Staff R&D Engineer - GPU hot job

    @ Synopsys Inc

    ๐Ÿ“Seongnam, South Korea ๐Ÿ‡ฐ๐Ÿ‡ท
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C/C++ algorithms
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    ASIC Digital Verification Engineer - Senior Staff

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
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    ASIC Physical Design Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC PNR STA
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    Principal ASIC Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Munich, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog Python
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    ASIC Digital Verification - Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
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    Sr Staff, ASIC Design Verification Engineer-13965

    @ Synopsys Inc

    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification UVM automation
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SystemVerilog Verilog Python
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    Principal Engineer- RTL Design

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    RTL ASIC EDA
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    ASIC Verification- Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Perl
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    ASIC Digital Design Engineer, Staff

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VCS Verdi UVM
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    FPGA Applications Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA Verilog SystemVerilog
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    RTL Design- Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SERDES ASIC
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    Product Engineer โ€“ HAV

    @ Synopsys Inc

    ๐Ÿ“Rungis, France ๐Ÿ‡ซ๐Ÿ‡ท
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    emulation FPGA SoC
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    Sr. Firmware Design Engineer-13999

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C Serdes
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    Principal Analog IC Design Engineer - 14913

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES CMOS SPICE
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    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC MIPI PCIe
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    Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES CMOS Verilog-A
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    Analog Design, Staff Engineer in Tan Binh district

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog IC mixed-signal
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    ASIC Digital Design, Sr Engineer - 14141 hot job

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Verilog VHDL
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    Staff Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES PAM4 FinFET
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    Senior Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES FinFET PAM4
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    ASIC Digital Design, Sr Staff Engineer - 13027

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC UVM SystemVerilog
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    Analog Layout Design, Staff Engineer in Hanoi

    @ Synopsys Inc

    ๐Ÿ“Hanoi, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Cadence Synopsys Calibre
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    Analog Design, Principal Engineer-13381

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    Verilog-A SystemVerilog TCL
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    Staff Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ contract
    analog CMOS SerDes
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    Staff/ Sr Staff RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog UVM
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    Senior Firmware Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C Serdes
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    HBM Design Verification Engineer, Principal hot job

    @ Synopsys Inc

    ๐Ÿ“Hsinchu City, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    UVM SystemVerilog DDRx
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    Analog Design, Sr Engineer in Tan Binh, HCMC hot job

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal PHY
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    SOC Engineering, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL2GDSII synthesis verification
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    SerDes IP Senior Analog Design Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
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    SerDes CMOS SPICE
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    Analog Layout Design, Sr Engineer in Danang

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Cadence Synopsys Mentor
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    AI machine EDA
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    Analog Layout Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hanoi, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    layout PLL DRC
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    SOC Engineering, Sr Engineer in District 7

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC SOC Synthesis
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    Senior Staff Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ contract
    analog SerDes SPICE
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    RTL Design and Signoff, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    RTL LINT CDC
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    SOC Engineering, Sr/ Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC Fusion TCL
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    ASIC Digital Design, Sr Engineer - DFT

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    DFT Scan ATPG
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    Analog Layout Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Viet Nam
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    layout AIB PLL
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    ASIC Digital Design Staff Engineer - RTL

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification SystemVerilog DDR
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    Analog Layout Design, Staff Engineer in Danang

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Cadence Synopsys Calibre
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    Architect- ASIC Verification IP Development hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM DDR
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    Analog Design, Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Transmission SPICE DDR
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Transmission SPICE DDR
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Transmission SPICE DDR
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    Staff ASIC Engineer โ€“ DFT

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT ATPG Spyglass
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    ASIC Digital Design, Principal Engineer-13487

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    Verilog SystemVerilog DDR
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    ASIC Digital Design Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Perl
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes CMOS SPICE
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    Firmware Development & Validation Engineer - 12947

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ Python Jenkins
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    DDR Design Verification, Principal Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Hsinchu City, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    DDR5 LPDDR6 UVM
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    ASIC Digital Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC verification Interface
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    ASIC Digital Design, Principal Engineer - 13372 hot job

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UVM
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    SOC RTL Engineering - Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SoC RTL Lint
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    FPGA Emulation Application Engineer

    @ Synopsys Inc

    ๐Ÿ“Zapopan, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA VHDL Verilog
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    Staff Embedded Systems Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ SoC SystemC
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    SoC Firmware-Hardware Validation Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog silicon Python
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    Staff RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog USB PCIe
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    Software Engineer - Firmware

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware Linux RTOS
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    ASIC Digital Design, Principal Engineer - 13121

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Python
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    DDR Analog Design Architect

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog IC CMOS
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    ASIC Digital Design, Principal Engineer - 13030 hot job

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC SerDes UVM
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC VLSI PnR
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    Analog Layout Engineer - Staff

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    layout CMOS FINFET
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes CMOS ADC
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    High-Speed Analog Layout Engineer - Staff

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog MixedSignal Cadence
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    Senior Staff Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SERDES CMOS Verilog-A
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Pavia, Italy ๐Ÿ‡ฎ๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C Verilog Python
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    Principal SoC Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    UVM PCIe Ethernet
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    Analog Design, Senior Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ internship
    analog SPICE circuit
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Verilog SystemVerilog
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    ASIC Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SystemVerilog VMM OVM
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    SOC Engineering, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC FPGA SystemVerilog
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    Senior Staff Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal PCIe
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    PCIe Design Verification Engineer, Staff

    @ Synopsys Inc

    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    PCIe CXL UVM
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    Analog Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog ESD FinFet
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    ASIC Digital Verification Engineer, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    Principle RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    Serdes DDR PHY
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL PCIe DDR
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    SOC Verification Architect

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UVM
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    Analog Layout Engineer- Staff

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    layout Analog CMOS
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FinFET SerDes CMOS
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    ASIC Digital Design, Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SERDES Verilog
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FinFET SerDes CMOS
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS DDR IP
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    Analog Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    Analog Mixed Signal
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    Staff SOC Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL LINT CDC
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    ASIC Digital Design, Principal Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC Verilog VHDL
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    Embedded Systems Simulation Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Linux Python
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    Analog Layout Engineer - Principal

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    analog mixed-signal SERDES
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    Analog Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Analog Mixed-signal HSPICE
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    Analog Layout Engineer - Senior

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog Mixed-Signal CMOS
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    ASIC Physical Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC GDSII CMOS
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS DDR HBM
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    Analog Design, Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal circuit
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    Senior Staff Engineer - Analog Layout

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog Layout CMOS
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    DFT ATPG RTL
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    Analog Design Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š junior
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    Analog Design Sr Engineer

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    SOC Engineering, Sr Staff Engineer

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    UVM Coverage Verification
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    PCIe Design Verification Engineer, Sr Engineer

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    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
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    PCIe CXL UVM
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    Analog Design, Staff Engineer

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    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    RTL Design and Signoff - Staff Engineer

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    ASIC Digital Design Engineer, Senior Staff

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    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
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    ASIC PCIe Verilog
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    ASIC Verification, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    VLSI Ethernet AMBA
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    Analog Design, Principal Engineer

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    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    analog mixed-signal FinFET
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    ASIC Digital Design, Sr Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Senior Analog Layout Engineer

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    AI Compiler Engineer, Staff

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    ๐Ÿ“Eindhoven, Netherlands ๐Ÿ‡ณ๐Ÿ‡ฑ
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    compiler optimization LLVM
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    Analog Design, Sr Engineer

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    ๐Ÿ“Gyumri, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    analog circuits PPA
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    Analog Design, Staff Engineer

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    ๐Ÿ“Pavia, Italy ๐Ÿ‡ฎ๐Ÿ‡น
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    SERDES Verilog-A TCL
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    Analog Design, Principal Engineer

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    ๐Ÿ“Pavia, Italy ๐Ÿ‡ฎ๐Ÿ‡น
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    SERDES PAM4 ADC
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    Analog Design, Sr Staff Engineer

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    ๐Ÿ“Pavia, Italy ๐Ÿ‡ฎ๐Ÿ‡น
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    SerDes Verilog-A MATLAB
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    Analog Design, Principal Engineer hot job

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    PLL SERDES CMOS
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    ASIC Digital Design, Sr Engineer

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    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
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    RTL Verilog SerDes
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    ASIC Digital Design, Sr Staff Engineer-8569

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    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    Verilog SystemVerilog UVM
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    SOC Design Verification Engineer, Principal

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    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SystemVerilog UVM PCIe
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    Senior Staff ASIC Verification Engineer

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    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
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    ASIC UVM verification
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    ASIC Physical Design, Staff Engineer hot job

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    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    Timing Synthesis Place
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    ASIC Digital Design, Sr Staff Engineer-10718 hot job

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    ๐Ÿ“Boxborough, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    ASIC Verilog PERL
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    Senior SOC Design Verification Engineer

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    ๐Ÿ“Zapopan, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
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    SoC UVM SystemVerilog
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    Staff ASIC Digital Design

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Verilog SerDes
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    ASIC Digital Design Sr. Staff Engineer

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC RTL CDC
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    ASIC Digital Design, Sr Staff Engineer

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    ๐Ÿ“Bucharest, Romania ๐Ÿ‡ท๐Ÿ‡ด
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    SystemVerilog UVM Simulation
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    ASIC Digital Verification, Senior Staff Engineer

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    SystemVerilog UVM SerDes
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    Senior Staff ASIC Digital Design

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    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Verilog DSP
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    Senior Staff ASIC Digital Design

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    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    Verilog VCS DFT
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    Analog Design, Staff Engineer hot job

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    CMOS circuit PAM4
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    Firmware Design Engineer, Staff

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    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    C/C++ firmware SoCs
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    RTL Design and Signoff - Senior Staff Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    RTL LINT CDC
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    Program Engineering Management

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    SoC IP analog
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    SOC Engineering, Staff Engineer hot job

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog VHDL Unix
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    ASIC Digital Design, Engineer

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    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    USB DDR PCIe
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    Principal Engineer- ASIC Verification

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC PCIe CXL
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog SystemVerilog SerDes
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    HBM Design Verification Engineer, Sr Staff

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    ๐Ÿ“Hsinchu City, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
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    verification UVM SystemVerilog
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    ASIC Physical Design, Staff Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC DDR timing
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    ASIC Verification, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog VCS PCIe
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
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    SystemVerilog UVM VCS
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    Analog Design, Staff Engineer

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    ๐Ÿ“Seongnam, South Korea ๐Ÿ‡ฐ๐Ÿ‡ท
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    SerDes CMOS SPICE
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    Staff Analog Design Engineer

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    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    analog SERDES CMOS
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    Analog Design, Staff Engineer

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    analog mixed-signal IC
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    Analog Design Engineer

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    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    analog SerDes CMOS
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    Analog Design, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    HSPICE Primesim VCS
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    Staff Analog Design Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Analog SPICE EDA
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    ASIC Design Engineer hot job

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    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
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    RTL UVM SystemVerilog
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    Senior Staff GPU R&D Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    GPU CUDA OpenCL
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    UVM SystemVerilog RISC
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    ASIC Digital Verification, Sr. Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
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    TCL PYTHON PERL
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    ASIC Digital Design, Sr Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC Verilog SerDes
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog Verilog C++
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    ASIC Digital Verification, Sr Staff Engineer

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    ๐Ÿ“Pavia, Italy ๐Ÿ‡ฎ๐Ÿ‡น
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    Verilog SystemVerilog UVM
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    Senior Staff ASIC Design Engineer

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Verilog SerDes
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Bucharest, Romania ๐Ÿ‡ท๐Ÿ‡ด
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    SystemVerilog UVM Simulation
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    ASIC Digital Design, Staff Engineer - 10655

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC SerDes CDR
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    ASIC Physical Design Engineer, Sr Staff hot job

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    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    GDSII Tcl Perl
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Moreira, Brazil ๐Ÿ‡ง๐Ÿ‡ท
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    RTL PCIe USB
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    ASIC Digital Design Engineer, Senior

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog VCS SerDes
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    ASIC Digital Design, Staff Engineer - RTL Design

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog VCS Scripting
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    Architect - ASIC Verification

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC PCIe CXL
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    Analog layout design

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    layout routing verification
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    Analog Design, Sr Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SERDES CMOS PLL
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    SOC Engineering, Staff Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    RTL SoC Synthesis
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    ASIC Physical Design, Sr Staff Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    RTL GDSII Python
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    ASIC Digital Design, Sr Staff Engineer

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    ๐Ÿ“Moreira, Brazil ๐Ÿ‡ง๐Ÿ‡ท
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    ASIC Verilog VHDL
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    ASIC Digital Design, Sr. Staff

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Verilog DSP
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    ASIC Digital Verification, Staff Engineer

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    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    verification SystemVerilog UVM
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    Sr Staff, ASIC Digital Design Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC Verilog SystemVerilog
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    ASIC Physical Design, Sr Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC Physical Design, Sr Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC Digital Verification Sr Engineer

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    ๐Ÿ“Eindhoven, Netherlands ๐Ÿ‡ณ๐Ÿ‡ฑ
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    Analog design, Senior Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    UVM SystemVerilog PCIe
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    ASIC Digital Design, Sr Staff Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog Verilog UVM
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog RISC DSP
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    ASIC Digital Design, Sr Staff Engineer

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    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    Analog Design, Staff Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    CMOS DSP Verilog
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    Senior Analog Design Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    CMOS DDR ASIC
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    Senior Analog Design Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SerDes CMOS spice
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    Analog Design, Staff Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    Analog Hspice Pythonscripting
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    Analog Design, Sr Engineer

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    ๐Ÿ“Gdansk Metropolitan Area, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
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    CMOS SERDES IC
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    Analog Layout Design, Staff Engineer in Da Nang

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    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    Cadence Synopsys Mentor
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    Analog Design, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SerDes CMOS SPICE
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    Analog Design, Principal Engineer hot job

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SERDES PAM4 FinFET
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    Analog Design, Staff Engineer

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    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
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    ASIC SERDES Synthesis
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    ASIC Verification, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog VCS AMBA
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    ASIC Digital Design, Engineer

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    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
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    VLSI Verilog SystemVerilog
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    ASIC Digital Design, Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    Verilog VCS Scripting
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    ASIC Digital Design Engineer, Architect

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    RTL Verilog SystemVerilog
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    Senior Staff ASIC Digital Design Engineer - 9290

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    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Digital Design, Manager

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    ASIC SystemVerilog Verilog
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    ASIC Digital Verification Engineer

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    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
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    UVM SystemVerilog C
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    Senior Staff ASIC Design Engineer

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    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SystemVerilog UVM DDR
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    DDR Design Verification Engineer

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    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
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    Verilog VHDL SystemVerilog
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    Staff ASIC Digital Design Engineer - 6546 hot job

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    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Verilog SerDes
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    ASIC Digital Design, Sr Engineer

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    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
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    ASIC Sr Staff Engineer

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    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Physical Design, Staff Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    DDR HBM ICC2
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    FPGA/ASIC Validation, Staff Engineer

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    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SoC Engineering Sr Staff Engineer

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    ๐Ÿ“Plano, TX, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    RTL GDSII Synopsys
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    Principal Analog Design Engineer

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    ๐Ÿ“Boxborough, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    FinFET SerDes DAC
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    Analog Design, Staff Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    CMOS HSPICE PrimeSim
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    Principal Analog Design Engineer

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    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    FinFET ADC DAC
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    Analog Layout Design Engineer, Staff

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Analog Mixed-Signal DRC
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    Senior Staff Analog Design Engineer hot job

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    analog mixed-signal circuit
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    Analog Design, Senior Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    HSPICE PrimeSim ADCs
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    Analog Design, Senior Engineer

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    ๐Ÿ“Plymouth, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    analog simulation mixed-signal
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    Sr Firmware Design Engineer - 7364

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    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    firmware C Serdes
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    SOC Physical Design Engineer, Sr. Staff

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    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    SoC RTL GDSII
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    ASIC Physical Design, Sr Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š mid-level
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    ASIC VLSI GDSII
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    Sr Staff Engineer , Mixed Signal Analog Design hot job

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    CMOS PLL Regulators
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    Analog Design, Staff Engineer hot job

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    CMOS SerDes SPICE
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    Design Verification, Sr Staff Engineer in HCMC

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    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    VCS Verdi UPF
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    Sr Staff ASIC Verification Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog UVM DDR
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    RTL Design Engineer- High Speed IP

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog Spyglass PCIe
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    Analog Design Senior Engr in HCMC/ Da Nang / Hanoi

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    ๐Ÿ“Hanoi, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
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    Analog CMOS Cadence
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    Analog Design Automation, Sr Engineer

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    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    Python SQL automation
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    ASIC Digital Design, Staff Engineer - 9162

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    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    ASIC Verilog VCS
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    ASIC Digital Design, Sr Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog UVM Verilog
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    SOC Engineering, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Verilog SystemVerilog UVM
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    RTL Design Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    Analog Design, Sr Engineer

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    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SerDes ADC DAC
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    Analog Design Staff Engineer

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    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    analog mixed-signal layout
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    ASIC Digital Design, Staff Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    Verilog SystemVerilog FPGA
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    ASIC Digital Verification Design, Staff Engineer

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    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    SystemVerilog Verilog UVM
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    ASIC Verification- Principal Engineer

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    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    SystemVerilog VCS AMBA
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    Analog Design, Sr Staff Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    Analog Mixed PCIe
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    Analog Design, Staff Engineer

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    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
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    PLLs Hspice Pythons
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    NVM Analog Design Engineer, Staff

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    ๐Ÿ“Hsinchu City, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
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    NVM CMOS HSPICE
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    ASIC Digital Design, Sr. Staff Engineer-10658

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    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
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    C Verilog PCIe
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    SOC Engineering, Principal Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    UVM PCIe Ethernet
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    Analog Design, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
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    SOC Physical Design Engineer, Sr Staff

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    ๐Ÿ“San Diego Metropolitan Area, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    Design Verification, Principal Engineer

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    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
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    SystemVerilog VCS NC
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    ASIC Physical Design, Staff Engineer

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    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
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    DC ICC2 PT-SI
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    ASIC Digital Design, Sr Engineer

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    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
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    ASIC HDL RISC
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    Graduate Analog Design Engineer

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    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š entry-level
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    analog mixed-signal SerDes
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    Analog Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Analog IC Hspice
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    Analog Design, Staff Engineer - 9287

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SERDES CMOS SPICE
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    Analog Design, Staff Engineer - 10544

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes SPICE Verilog-A
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    GPU/HPC R&D Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    CUDA C/C++ Python
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    Hardware/FPGA Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA XILINX VHDL
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    Senior FPGA Development Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA C/C++ Verilog
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    Emulation|FPGA Engineer

    @ Synopsys Inc

    ๐Ÿ“Lisboa, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCIe DDR Zebu
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    Emulation|FPGA Engineer

    @ Synopsys Inc

    ๐Ÿ“Lisboa, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCIe DDR Zebu
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    DDR LPDDR UVM
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    ASIC Digital Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    Verilog digital ASIC
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    ASIC Verification, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC PCIe CXL
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    ASIC Digital Design/Graduate Electronic Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog VHDL
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    ASIC Physical Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Tcl Shell C
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    ASIC Digital / Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC PCIe CXL
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    Senior ASIC Physical Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC GDSII RTL
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    Staff ASIC RTL Digital Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog Synthesis
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    ASIC Digital Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog PERL TCL
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    Sr. Staff ASIC Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM Verilog VHDL
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    Applications Engineer 4908

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC RTL PCIe
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Pavia, Italy ๐Ÿ‡ฎ๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Verilog DSP
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    Sr, Staff ASIC Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog VHDL
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    ASIC Digital Verification, Staff Engineer hot job

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Unix
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    Staff ASIC Verification Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog VHDL
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    ASIC Digital Design Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Pavia, Italy ๐Ÿ‡ฎ๐Ÿ‡น
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC Verilog VCS
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    FPGA Digital Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Porto Salvo, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    VHDL Verilog FPGA
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    ASIC Digital Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Verilog FPGA Python
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Aschheim, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC RTL Verilog
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    ASIC DFT, Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    DFT JTAG ATPG
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    ASIC Digital Verification Engineer, Principal

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC PCIe CXL
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    ASIC Verification Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UVM
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    Embedded Software Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C Bash Python
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    Analog Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog mixed-signal SerDes
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    Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes SPICE CMOS
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    Lead Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog Mixed-signal PCIe
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    Analog Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Gdansk Metropolitan Area, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    analog SPICE UNIX
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    Analog Layout Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    layout CMOS FinFET
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    Senior Analog Layout Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    EDA Cadence Virtuoso
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Analog ESD JEDEC
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    Analog Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    IC Design Simulation
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    Analog Design - STA Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog CMOS timing
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    Analog Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog PHY JEDEC
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS DDR ASIC
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    Analog Design Engineer, Senior

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS Verilog-A HSPICE
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    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS ESD DDR
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    High-Speed Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SerDes SPICE PLLs
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    Top-level Analog Layout Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Cadence Synopsys Mentor
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    Analog Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Analog Hspice TCL
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    Senior QA Engineer โ€“ Embedded Memory

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Python Tcl Perl
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    Embedded Software Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C Bash Python
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    Staff Embedded Memory Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SRAM CMOS FinFET
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    Embedded Memory Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS SRAM EDA
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    ASIC Digital Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification VMM OVM
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    ASIC Physical Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    IC RTL GDSII
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    RTL Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog Perl C
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    ASIC Digital Design, Staff Engineer - 9291

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog Verdi UVM
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    ASIC Digital Design, Staff Engineer - 9177

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ firmware SerDes
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    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Kanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL CDC
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    Design Verification, Sr Staff Engineer in HCMC

    @ Synopsys Inc

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SystemVerilog VCS
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    ASIC Digital Verification, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    SOC Design Verification Engineer, Senior Staff

    @ Synopsys Inc

    ๐Ÿ“Zapopan, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC UVM System
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog Mixed-Signal SerDes
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog SERDES CMOS
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Gdansk Metropolitan Area, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS SerDes IC
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    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS JEDEC DDR
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    Analog Design Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Yerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog Circuit CMOS
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    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC DRC LVS
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    ASIC Physical Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DC ICC2 PT-SI
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    ASIC Digital Design, Principal Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DDR LPDDR UVM
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    ASIC Digital Design, Engineer

    @ Synopsys Inc

    ๐Ÿ“Tokyo, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    VLSI System Verilog
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    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Verilog SERDES
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    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC RTL Verilog
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  • Expired
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    Analog Design, Staff Engineer - 8683

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog DDR CMOS
    View details
    View Analog Design, Staff Engineer - 8683
  • Expired
    Synopsys Inc logo

    Analog Design, Sr. Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog SPICE EDA
    View details
    View Analog Design, Sr. Staff Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog PHY JEDEC
    View details
    View Analog Design, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    Principal Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    PCIe SerDes LDO
    View details
    View Principal Analog Design Engineer
  • Expired
    Synopsys Inc logo

    Analog Design Engineer - Da Nang

    @ Synopsys Inc

    ๐Ÿ“Da Nang City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    IC AMS PLL
    View details
    View Analog Design Engineer - Da Nang
  • Expired
    Synopsys Inc logo

    Senior Embedded Systems Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ SoC SystemC
    View details
    View Senior Embedded Systems Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Sr Staff Engineer - 10873

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS PLL VCO
    View details
    View Analog Design, Sr Staff Engineer - 10873
  • Expired
    Synopsys Inc logo

    RTL design, Staff Engineer in Hanoi/ HCMC / Danang

    @ Synopsys Inc

    ๐Ÿ“Hanoi, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL ASIC VCS
    View details
    View RTL design, Staff Engineer in Hanoi/ HCMC / Danang
  • Expired
    Synopsys Inc logo

    ASIC Digital Design Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Dublin, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC IP Serdes
    View details
    View ASIC Digital Design Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Deign, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DDR PCIE UVM
    View details
    View ASIC Digital Deign, Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Staff Engineer - 9182

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Verilog SystemVerilog
    View details
    View ASIC Digital Design, Staff Engineer - 9182
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Staff Engineer - 9185

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Verilog SystemVerilog
    View details
    View ASIC Digital Design, Staff Engineer - 9185
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog RISC DSP
    View details
    View ASIC Digital Design, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Staff Engineer - 9184

    @ Synopsys Inc

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC Verilog SystemVerilog
    View details
    View ASIC Digital Design, Staff Engineer - 9184
  • Expired
    Synopsys Inc logo

    ASIC Digital Verification Engineer, Architect

    @ Synopsys Inc

    ๐Ÿ“Nepean, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC PCIe UCIe
    View details
    View ASIC Digital Verification Engineer, Architect
  • Expired
    Synopsys Inc logo

    ASIC Physical Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC Synthesis Verification
    View details
    View ASIC Physical Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design Verification, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM PCIe
    View details
    View ASIC Digital Design Verification, Staff Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Wuhan, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    HDL RISC DSP
    View details
    View ASIC Digital Design, Sr Engineer
  • Expired
    Synopsys Inc logo

    SOC Engineering, Sr Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Plano, TX, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC FPGA SystemVerilog
    View details
    View SOC Engineering, Sr Staff Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI CMOS DDR
    View details
    View Analog Design, Sr Engineer
  • Expired
    Synopsys Inc logo

    Staff Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS PLL EDA
    View details
    View Staff Analog Design Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog AMS PLLs
    View details
    View Analog Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    Principal Analog Design Engineer

    @ Synopsys Inc

    ๐Ÿ“Mississauga, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    FinFET SERDES DAC
    View details
    View Principal Analog Design Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog CMOS SPICE
    View details
    View Analog Design, Staff Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Analog PLL VCO
    View details
    View Analog Design, Sr Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI ASIC DDR
    View details
    View Analog Design, Sr Engineer
  • Expired
    Synopsys Inc logo

    IP Firmware Development, Staff Engineer

    @ Synopsys Inc

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Firmware IP Development
    View details
    View IP Firmware Development, Staff Engineer
  • Expired
    Synopsys Inc logo

    Senior Embedded Systems Engineer

    @ Synopsys Inc

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ SoC SystemC
    View details
    View Senior Embedded Systems Engineer
  • Expired
    Synopsys Inc logo

    ASIC Digital Design Engineer, Principal

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š principal
    โฑ๏ธŽ
    ASIC RTL HBM
    View details
    View ASIC Digital Design Engineer, Principal
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Staff Engineer - 9730

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog HDL FPGA
    View details
    View ASIC Digital Design, Staff Engineer - 9730
  • Expired
    Synopsys Inc logo

    ASIC Digital Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“Moreira, Portugal ๐Ÿ‡ต๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog MIPI
    View details
    View ASIC Digital Design, Sr Engineer
  • Expired
    Synopsys Inc logo

    Analog Design, Sr Engineer

    @ Synopsys Inc

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog sensors layout
    View details
    View Analog Design, Sr Engineer
  • Expired
    Synopsys Inc logo

    DDR Analog Design Architect

    @ Synopsys Inc

    ๐Ÿ“Markham, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog CMOS DDR
    View details
    View DDR Analog Design Architect
  • Expired
    Synopsys Inc logo

    Analog IC Design Architect

    @ Synopsys Inc

    ๐Ÿ“Sunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog Verilog UVM
    View details
    View Analog IC Design Architect
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Company Info
Employees 10001+
Founded 1986
Type Public
Stock SNPS
Glassdoor 4.2
Connect
Active Hiring Locations
๐Ÿ“ Bengaluru, Karnataka, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ 6
๐Ÿ“ Noida, Uttar Pradesh, India, India ๐Ÿ‡ฎ๐Ÿ‡ณ 4
๐Ÿ“ Yerevan, Yerevan, Armenia, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ 2
๐Ÿ“ Boxborough, MA, United States ๐Ÿ‡บ๐Ÿ‡ธ 2
๐Ÿ“ Kanata, Ontario, Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ 1
Top Roles
ASIC Design Engineer (10) Analog Design Engineer (6) FPGA Engineer (4) Embedded Systems Engineer (3) Hardware Engineer (1)
Key Skills
Verilog SystemVerilog ASIC Python UVM PCIe CMOS RTL
Seniority Levels
senior (18) mid-level (5) entry-level (2)
Work Arrangement
On-site (25)

About Synopsys Inc

Synopsys Inc develops electronic design automation (EDA) software and semiconductor intellectual property (IP) products from its headquarters in Mountain View, California. Its tools support the design of complex integrated circuits and systems-on-chip, with notable products including Design Compiler and PrimeTime, which are widely used in the semiconductor industry. Engineering disciplines at Synopsys include digital and analog design, verification, and physical design. Engineers solve challenges related to power, performance, and area optimization in chip design. With a workforce of approximately 15,000 employees, Synopsys operates globally, providing a comprehensive suite of tools that streamline the design process for leading semiconductor companies.

Synopsys Inc Career Opportunities

Synopsys Inc currently has 25 active embedded systems positions spanning 9 countries. All positions are on-site, typical for hardware-focused roles requiring lab access and equipment. Recognized as a top-tier employer (80.0/100), Synopsys Inc offers competitive compensation and strong career development paths in embedded engineering.

Synopsys Inc Hiring Trends

* Data represents job posting activity over the past 6 months: Feb 2026 through Jul 2026

Synopsys Inc's hiring pace has moderated recently (15 openings this month vs 52 last month), which is common after major hiring pushes or as projects move from development to deployment phases.

Over the past 6 months, Synopsys Inc averaged 53.8 job postings per month, with peak hiring in May 2026 (91 openings). For embedded systems roles, hiring activity typically correlates with product development cycles, especially for firmware teams during pre-production phases and hardware engineers during prototyping.

Current Month
15 jobs

๐Ÿ“‰ -71% change

6-Month Average
53.8 jobs/month

Consistent hiring velocity

Peak Activity
91 jobs

May 2026

Required Skills at Synopsys Inc

Verilog is the most in-demand skill at Synopsys Inc, appearing in 25% of all job listings (past and present). This skill is important but not universal, indicating diverse technical needs across different product lines or teams.

Synopsys Inc's technology stack spans 376 distinct skills and tools, reflecting the multifaceted nature of embedded systems development. The broad technical diversity (376 technologies) suggests work on complex, multi-domain projects requiring both hardware and software expertise.

Verilog
25% of roles
25%
SystemVerilog
24% of roles
24%
ASIC
23% of roles
23%
Python
21% of roles
21%
UVM
20% of roles
20%
PCIe
18% of roles
18%
CMOS
17% of roles
17%
RTL
16% of roles
16%
DDR
15% of roles
15%
SerDes
14% of roles
14%
TCL
11% of roles
11%
EDA
9% of roles
9%

Engineers joining Synopsys Inc should combine depth in key areas with adaptability. The mix of hardware skills (PCB design, schematics) and firmware expertise (RTOS, embedded C) indicates full-stack embedded development where engineers work across the hardware-software boundary. Candidates with adjacent skills (version control, testing frameworks, communication protocols) typically advance faster by contributing across the development lifecycle.

Engineering Roles at Synopsys Inc

Synopsys Inc's primary hiring focus is ASIC Design Engineer with 10 open positions. High-volume recruitment for a single role type typically indicates either a growing team building similar capabilities or a newly formed department scaling rapidly.

Multiple openings in the same discipline create advantages for new hires: stronger peer support networks, established onboarding processes, and clearer career progression paths as the team matures. Engineers often find collaborative environments more conducive to professional growth.

ASIC Design Engineer
10 positions (40%)
10
Analog Design Engineer
6 positions (24%)
6
FPGA Engineer
4 positions (16%)
4
Embedded Systems Engineer
3 positions (12%)
3
Hardware Engineer
1 position (4%)
1
Embedded Software Engineer
1 position (4%)
1

Experience level distribution: 72% of openings target senior-level engineers. The range across 3 experience levels suggests a well-balanced team structure with opportunities for both experienced engineers and those earlier in their careers.

Where Synopsys Inc is Hiring

Synopsys Inc operates across 22 countries with 76 total hiring locations. Multi-geography recruitment typically indicates either distributed engineering teams, expansion into new markets, or proximity to manufacturing and customer operations.

Bengaluru, India serves as a primary hiring hub with 14% of all roles (93 positions). Engineering capabilities are distributed relatively evenly across locations, suggesting a genuinely multi-site development model rather than a single headquarters-centric approach.

๐Ÿ“
Bengaluru, Karnataka
6 active jobs
6
๐Ÿ“
Noida, Uttar Pradesh
4 active jobs
4
๐Ÿ“
Yerevan, Yerevan
2 active jobs
2
๐Ÿ“
Boxborough, MA
2 active jobs
2
๐Ÿ“
Kanata, Ontario
1 active job
1
๐Ÿ“
Mississauga, Ontario
1 active job
1
๐Ÿ“
Ho Chi Minh City, Ho Chi Minh City
1 active job
1
๐Ÿ“
Eindhoven, North Brabant
1 active job
1
๐Ÿ“
Raanana, Center District
1 active job
1
๐Ÿ“
Sunnyvale, CA
1 active job
1
๐Ÿ“
Hillsboro, OR
1 active job
1
๐Ÿ“
Dublin, County Dublin
1 active job
1
๐Ÿ‡น๐Ÿ‡ผ
Hsinchu City, Taiwan
1 active job
1
๐Ÿ“
La Jolla Amago, CA
1 active job
1
๐Ÿ“
Ottawa, Ontario
1 active job
1
๐Ÿ‡ฎ๐Ÿ‡ณ
Bengaluru, India
93 previous jobs
๐Ÿ‡ฎ๐Ÿ‡ณ
Hyderabad, India
54 previous jobs
๐Ÿ‡ฎ๐Ÿ‡ณ
Noida, India
44 previous jobs
๐Ÿ‡จ๐Ÿ‡ฆ
Mississauga, Canada
24 previous jobs
๐Ÿ‡ป๐Ÿ‡ณ
Ho Chi Minh City, Vietnam
23 previous jobs
๐Ÿ‡ฆ๐Ÿ‡ฒ
Yerevan, Armenia
23 previous jobs
๐Ÿ‡จ๐Ÿ‡ฆ
Markham, Canada
20 previous jobs
๐Ÿ‡ต๐Ÿ‡น
Moreira, Portugal
19 previous jobs

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