Staff/ Sr Staff RTL Design Engineer

Key Responsibilities

• RTL logic development in Verilog RTL modeling language
• Digital design validation and functional verification
• Logic synthesizes, Static Timing Analysis and fault coverage reports
• DFT expertise for memories and logic test
• Finding and pinpointing design timing and DFT functional issues
• Knowledge in modeling languages and Firmware use flows with MCU
• Scripting capabilities in Tcl or other scripting languages
• Define architecture design, logic design, test bench design, and embedded Software functions for test and system analytics.
• Develop and maintain collateral: test suites, protocol documentation, debug guides.
• Collaborate with R&D and marketing to define new features, enhancements, and roadmap alignment.
• Deliver product training sessions, manage CASE resolution, ensuring TAT metrics are consistently met or exceeded

Skills & Qualifications

• Requires 5-10 years of experience in RTL coding and RTL Designing
• Requires knowledge and experience with RTL simulation, logic synthesis, and timing verification tools
• Deep expertise in UVM, SystemVerilog , and protocol verification.
• Hands-on experience with VIPs and Transactors in simulation/emulation environments.
• Strong understanding of DFT architectures, interconnects, and cache coherency protocols.
• Familiarity with debug tools like Verdi, and performance analysis workflows.