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Intel

Intel

Delivering innovative computing solutions for a connected world.

๐Ÿ“ Santa Clara, California

35 Open Positions
8 Active Locations
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About Intel

Intel manufactures microprocessors, chipsets, and integrated circuits, headquartered in Santa Clara, California. Its Core and Xeon processor families serve a wide range of markets, including personal computing, data centers, and AI applications. Engineering disciplines at Intel include hardware design, software development, and systems architecture. Engineers tackle challenges in power efficiency, performance optimization, and integration of advanced technologies like AI and machine learning. With over 110,000 employees and multiple design and manufacturing sites worldwide, Intel is a leader in semiconductor innovation.

Current Job Openings

35 jobs

All Intel Job Openings

  • Intel logo

    Senior RTL Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SerDes PIPE
  • Intel logo

    Senior CPU RTL Design Engineer โ€“ Power Management hot job

    @ Intel

    ๐Ÿ“Phoenix, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SystemVerilog Verilog
  • Intel logo

    RTL Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SerDes
  • Intel logo

    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    firmware IPU Linux
  • Intel logo

    CPU RTL Design Engineer

    @ Intel

    ๐Ÿ“Phoenix, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
  • Intel logo

    Triton Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Ottawa, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C++ Python
  • Intel logo

    ASIC, SOC, Foundry market research consultant hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ contract
    Ethernet PCIe UCIe
  • Intel logo

    Quantum Error Correction Software Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    quantum correction protocols
  • Intel logo

    Package and PCB Layout Eng

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RF PCB DFM
  • Intel logo

    EDA Tools Hardware Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    EDA CAD Scripting
  • Intel logo

    EDA Tools Hardware Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC CTS Innovus
  • Intel logo

    Sr. CPU RTL Front End Methodology Engineer

    @ Intel

    ๐Ÿ“Phoenix, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL microarchitecture AI
  • Intel logo

    GPU Compiler Engineer Fixed-Term

    @ Intel

    ๐Ÿ“Munich, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ contract
    GPU C++ LLVM
  • Intel logo

    PCB Layout Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ contract
    Cadence PCB HDI
  • Intel logo

    Senior Analog Design Engineer hot job

    @ Intel

    ๐Ÿ“Chandler, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PLL ADC PCIe
  • Intel logo

    Analog Design Engineer

    @ Intel

    ๐Ÿ“Chandler, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    analog simulation Cadence
  • Intel logo

    RTL Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SerDes
  • Intel logo

    Analog Design Engineering Manager hot job

    @ Intel

    ๐Ÿ“Chandler, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ADC DAC PLL
  • Intel logo

    Senior Linux Kernel Developer hot job

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Linux C PCIe
  • Intel logo

    Senior CPU RTL Design Engineer

    @ Intel

    ๐Ÿ“Hillsboro, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL microarchitecture simulation
  • Intel logo

    Director, SoC Design Engineering hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM PCIe
  • Intel logo

    Graduate Talent

    @ Intel

    ๐Ÿ“Kulim, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ contract
    PHY IC simulation
  • Intel logo

    RTL Design & Verification Engineer โ€“ AI

    @ Intel

    ๐Ÿ“Haifa, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
  • Intel logo

    Device Driver validation Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ contract
    driver validation Linux
  • Intel logo

    Device Driver validation Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ contract
    driver Linux Chrome
  • Intel logo

    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM OVM
  • Intel logo

    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM C++
  • Intel logo

    CPU RTL Design Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
  • Intel logo

    EDA Tools Hardware Engineer

    @ Intel

    ๐Ÿ“Hsinchu, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    EDA Python Perl
  • Intel logo

    Senior AI SoC Design Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC SystemVerilog RTL
  • Intel logo

    Firmware HW Integration Validation Lead

    @ Intel

    ๐Ÿ“Hillsboro, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C C++ SystemC
  • Intel logo

    WiFi Firmware PHY Engineering Student

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ internship
    WiFi C C++
  • Intel logo

    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware C Python
  • Intel logo

    AI SoC Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL SystemVerilog SoC
  • Intel logo

    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ contract
    SystemVerilog UVM AI
    • Previously posted positions that may provide insight into Intel's hiring patterns
  • Expired
    Intel logo

    EDA Tools Hardware Engineer

    @ Intel

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Synthesis Place Route
    View details
  • Expired
    Intel logo

    Firmware Validation Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware Python validation
    View details
  • Expired
    Intel logo

    SoC Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC RTL IP
    View details
  • Expired
    Intel logo

    SoC RTL Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SoC ASIC
    View details
  • Expired
    Intel logo

    Silicon Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    UEFI BIOS PCIe
    View details
  • Expired
    Intel logo

    ASIC and Custom Silicon Sales Leader hot job

    @ Intel

    ๐Ÿ“Phoenix, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC silicon semiconductor
    View details
  • Expired
    Intel logo

    Embedded WiFi/Network DevOps Developer Student

    @ Intel

    ๐Ÿ“Jerusalem, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    DevOps Jenkins Docker
    View details
  • Expired
    Intel logo

    RTL Design Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog VHDL
    View details
  • Expired
    Intel logo

    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Fort Collins, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
  • Expired
    Intel logo

    Firmware validation AI intern

    @ Intel

    ๐Ÿ“Minhang District, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ internship
    AI LangChain RAG
    View details
  • Expired
    Intel logo

    Triton Compiler Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Python LLVM
    View details
  • Expired
    Intel logo

    Firmware Development Engineer Intern

    @ Intel

    ๐Ÿ“Minhang District, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ internship
    C C++ Python
    View details
  • Expired
    Intel logo

    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Caen, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ internship
    firmware microcode FPGA
    View details
  • Expired
    Intel logo

    SoC RTL Verification Intern

    @ Intel

    ๐Ÿ“Minhang District, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    SystemVerilog UVM ARM
    View details
  • Expired
    Intel logo

    Firmware Validation Engineer

    @ Intel

    ๐Ÿ“Gdansk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ contract
    Python debugging validation
    View details
  • Expired
    Intel logo

    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM profiling
    View details
  • Expired
    Intel logo

    Compiler Engineer

    @ Intel

    ๐Ÿ“Gdansk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ LLVM Compiler
    View details
  • Expired
    Intel logo

    Principal Engineer, SoC Design Verification

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SoC verification emulation
    View details
  • Expired
    Intel logo

    RF Engineer

    @ Intel

    ๐Ÿ“Phoenix, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RF Cadence Python
    View details
  • Expired
    Intel logo

    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Fort Collins, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
  • Expired
    Intel logo

    Embedded OS Software Engineering Developer hot job

    @ Intel

    ๐Ÿ“Hillsboro, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTOS Bluetooth WiFi
    View details
  • Expired
    Intel logo

    Firmware Developer Engineering Intern

    @ Intel

    ๐Ÿ“Zapopan, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    firmware C Python
    View details
  • Expired
    Intel logo

    RF Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RFIC Cadence AMS
    View details
  • Expired
    Intel logo

    SoC Design Engineer Intern

    @ Intel

    ๐Ÿ“La Ribera, Costa Rica ๐Ÿ‡จ๐Ÿ‡ท
    ๐Ÿ“Š intern
    โฑ๏ธŽ internship
    SoC SystemVerilog Python
    View details
  • Expired
    Intel logo

    Firmware Development Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C/C++ RTOS
    View details
  • Expired
    Intel logo

    Compiler Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Python P4
    View details
  • Expired
    Intel logo

    Firmware Engineer

    @ Intel

    ๐Ÿ“Haifa, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Bluetooth C C++
    View details
  • Expired
    Intel logo

    Linux Kernel Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Linux Kernel FPGA
    View details
  • Expired
    Intel logo

    RTL Design Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog VHDL
    View details
  • Expired
    Intel logo

    Analog Design Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS PLLs LDOs
    View details
  • Expired
    Intel logo

    Silicon Firmware Development Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C UEFI BIOS
    View details
  • Expired
    Intel logo

    SOC Logic Design Engineer

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    RTL Verilog VHDL
    View details
  • Expired
    Intel logo

    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler GPU OpenCL
    View details
  • Expired
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    CPU Core Physical Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI synthesis timing
    View details
  • Expired
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    SoC Analog Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS analog mixed-signal
    View details
  • Expired
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    CPU Design Verification Lead/Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Emulation
    View details
  • Expired
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    CPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM FPGA
    View details
  • Expired
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    CPU Core Physical Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI timing lowpower
    View details
  • Expired
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    CPU Core Senior Physical Design Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI synthesis Tcl
    View details
  • Expired
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    Firmware Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    C++ Bluetooth WiFi
    View details
  • Expired
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    CPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    verification simulation SystemVerilog
    View details
  • Expired
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    CPU verification SystemVerilog
    View details
  • Expired
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification simulation debugging
    View details
  • Expired
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification simulation coverage
    View details
  • Expired
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    Soc Functional Validation Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC validation PCIe
    View details
  • Expired
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog GPU
    View details
  • Expired
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    SOC Design Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog GPU
    View details
  • Expired
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog VHDL
    View details
  • Expired
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog VHDL
    View details
  • Expired
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
  • Expired
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification UVM Verilog
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    Linux Kernel Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Linux Android FPGA
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    GPU Physical Design Engineer Lead

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    VLSI ASIC Unix
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    GPU SOC Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA silicon
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    SoC Physical Design Power Delivery Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PDN EM IR
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    SoC Physical Design Timing Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    STA Primetime TCL
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    SoC Physical Design Clocking Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC PLL DLL
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    SoC PnP Validation Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC OSPM Python
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    Linux Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Linux Kernel C
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU Linux Driver
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    SoC Functional Validation Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    SoC validation automation
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    Firmware Development Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    C/C++ ARM Linux
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    Firmware Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    firmware C/C++ SoC
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    Mixed Signal Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    SOC Logic Design Engineer hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    Senior GPU Validation Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU validation SystemVerilog
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    Lead CPU Design Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    CPU RTL microarchitecture
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    SOC Design Engineer โ€“ RTL design and Integration

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL SoC EDA
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM GCC
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Compiler LLVM GCC
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    firmware DSP architecture
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM SYCL
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM SYCL
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    LLVM C++ SYCL
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    LLVM C++ SYCL
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification testbench simulation
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Specman SystemVerilog PCIe
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    IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification UVM simulation
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    SoC Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    physical design synthesis
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    SoC Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    physical synthesis timing
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    SoC Power and Performance Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC CPU ITP
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM GCC
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    SoC Power Management Firmware Developer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC firmware power
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    SoC Power Management Firmware Developer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC Firmware Assembly
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    Silicon Firmware Development Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware FPGA UEFI
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    GPU software engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Linux RDMA
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    GPU software engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Linux MPI
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    CPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CPU UVM Python
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    CPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CPU UVM VCS
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    CPU Power Optimization Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CPU RTL automation
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    CPU Power Optimization Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    power optimization architecture
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    Graduate Talent

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ contract
    SoC PCH CPU
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    Graduate Talent

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ contract
    SoC PCH CPU
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    Senior DSP Algorithm Engineer hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DSP MATLAB wireless
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    GPU Logic Design Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SystemVerilog GPU
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SystemVerilog GPU
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    IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Synopsys
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    Verification Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM EDA
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    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM verification
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    Silicon Firmware Development Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware microcode FPGA
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    Senior RTL Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    Senior RTL Design Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU DirectX LibVA
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    GPU SOC firmware
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU Media DirectX
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C++ DirectX
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU Media ACCELERATION
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU DirectX LibVA
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU DirectX C++
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    Senior CPU Microcode Design Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    microarchitecture x86 firmware
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    Senior CPU Circuit Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS VLSI Memory
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification microarchitecture SystemVerilog
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    Senior CPU Microcode Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    x86 microarchitecture firmware
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    CPU Verification engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification CPU architecture
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    CPU Formal Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    formal verification microarchitecture
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification JasperGold SystemVerilog
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CPU verification microarchitecture
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    Junior CPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    CPU Digital SystemVerilog
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification microarchitecture SystemVerilog
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CPU UVM SystemVerilog
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    CPU Microcode Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    microarchitecture x86 firmware
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    CPU Microcode Design Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    microarchitecture x86 firmware
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    Junior CPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    CPU Verification SystemVerilog
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    CPU Circuit Design Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS EDA circuit
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    E-Core CPU Layout Design Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI CMOS TCL
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    Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    UVM SystemVerilog EDA
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    Mixed Signal Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog System Verilog UVM
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    Design Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verification UVM SystemVerilog
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    SoC/IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog Python
    View details
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    SoC/IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    UVM SystemVerilog verification
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    SoC Design Engineer Student

    @ Intel

    ๐Ÿ“San Jose, Costa Rica ๐Ÿ‡จ๐Ÿ‡ท
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    SoC System Verilog
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    SoC Functional Validation Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC validation simulation
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    Memory Systems Firmware Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    firmware C JEDEC
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    Compiler Engineer hot job

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    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    LLVM C++ Fortran
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM parallel
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware C Python
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM OpenMP
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM performance
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware RTOS JTAG
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    LLVM C++ SYCL
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM OpenMP
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ assembly LLVM
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    compiler LLVM C++
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM OpenMP
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    AI Robotics Engineer-

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ contract
    AI Robotics TensorFlow
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    Linux Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Linux Kernel Drivers
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    Linux Kernel Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Linux Drivers Kernel
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    Linux Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    Linux Kernel FPGA
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    Linux Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    Linux Kernel FPGA
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    Linux Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    Linux kernel FPGA
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    Linux Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Linux kernel FPGA
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    Firmware Validation Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware Validation Ethernet
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    Firmware Integrator and Developer

    @ Intel

    ๐Ÿ“Jerusalem District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware Linux RTOS
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    Firmware Validation Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Python FPGA PCIe
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    Senior Memory Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C JEDEC
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    Firmware Integrator and Developer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware integration C
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    Memory Systems Firmware Development Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    firmware C C++
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    firmware IPU Linux
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    Atom CPU Layout Design Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    VLSI CMOS Unix
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Perl Python SystemVerilog
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM AXI
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM verification
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    CPU Physical Design Engineer hot job

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CPU physical design
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    Senior CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CPU EDA GDS
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    Senior CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Cadence Synopsys RTL
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    SOC Emulation Validation Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    emulation RTL validation
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    CPU Pre-Silicon Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog RTL
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ LLVM Compiler
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    Senior Compiler Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM optimization
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification formal SoC
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification abstraction simulation
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    Senior Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification UVM AMBA
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM Fortran
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    CPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog C++
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM C++
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    Physical Design Engineer - CPU Core

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CPU VLSI timing
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    GPU Validation Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU PCIe C++
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
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    Senior CPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM Python C++
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    Senior CPU Pre-Silicon Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog C/C++
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    Soc Functional Validation Engineer hot job

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC PCIe firmware
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
    View details
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification simulation debugging
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    Silicon Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC System Verilog
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    Firmware Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C FPGA ARC
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    Graduate Talent

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ contract
    SoC CPU PCH
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    graphics validation debugging
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Python k8s GitHub
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM verification
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    SoC Power and Performance Validation Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC OSPM Power
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    Compiler Engineering Intern

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š intern
    โฑ๏ธŽ internship
    LLVM SYCL CUDA
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    RF Analog Layout Design Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RF Layout Cadence
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    RF Analog Layout Design Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RF VCO Cadence
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    SOC Emulation Validation Engineer

    @ Intel

    ๐Ÿ“Kulim, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    emulation RTL automation
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Vulkan DirectX
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    RTL Design & Micro-Architecture Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL SystemVerilog SoC
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    physical design Cadence
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
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    CPU Pre-Si Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL VHDL Verilog
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    IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
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    IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog UVM System
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    IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C++ Python
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    CPU Backend Design Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI EDA optimization
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    CPU RTL Design Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog V2K
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    CPU RTL Design Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SoC
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    CPU RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    CPU RTL Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog RTL
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    GPU Performance Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM Assembly OpenGL
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification SystemVerilog ASIC
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ LLVM compiler
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
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    C++ LLVM Compiler
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    Mixed Signal Design Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification VHDL Verilog
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    SOC Design Verification Engineer CG

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
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    Verilog Python UVM
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    End to End GPU AI Software Architect hot job

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    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
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    GPU AI firmware
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    End to End GPU AI Software Architect hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
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    GPU AI architecture
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    End to End GPU AI Software Architect hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
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    AI GPU firmware
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    verification JasperGold SystemVerilog
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    CPU Formal Verification Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification abstraction JasperGold
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    CPU Formal Verification Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification microarchitecture SystemVerilog
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    CPU Formal Verification Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification formal microarchitecture
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    CPU Formal Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification JasperGold Questa
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    System Firmware Engineer

    @ Intel

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware BIOS UEFI
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    Senior CPU RTL Design Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL microarchitecture silicon
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    Senior CPU RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL architecture silicon
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    SoC Verification Lead- Central Engineering Group

    @ Intel

    ๐Ÿ“Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC verification emulation
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    compiler LLVM parallel
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    GPU Performance Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    GPU APIs shaders
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    GPU Performance Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    GPU APIs RTL
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM C++
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL SystemVerilog UVM
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    GPU Validation Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU Validation PCIe
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog OVM
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    Firmware Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    BIOS Firmware UEFI
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    logic RTL GPU
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    AI/GPU SoC Lead hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š lead
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    SoC RTL Verilog
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    GPU Logic Design Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
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    Verilog SystemVerilog RTL
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    GPU Logic Design Engineer hot job

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    Senior Design Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SoC
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    Senior Design Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    AI/GPU SoC Lead hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC GPU RTL
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    AI/GPU SoC Lead hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA RTL Verilog
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    Compiler Engineering Intern

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ internship
    C++ OpenMP SYCL
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    Senior CPU Pre-Silicon Verification Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog EDA
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    Senior CPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM Python SystemVerilog
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    SoC FPGA emulation Intern

    @ Intel

    ๐Ÿ“Beijing, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    FPGA RTL SoC
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ LLVM OpenMP
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ LLVM optimization
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM optimization
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM optimization
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    IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Romania, Romania ๐Ÿ‡ท๐Ÿ‡ด
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Specman SystemVerilog PCIe
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    SoC PnP Validation Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC OSPM Python
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM RTL
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    Compiler Engineering Intern

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š intern
    โฑ๏ธŽ internship
    C++ clang compilers
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    GPU SOC Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA Verilog
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    SOC Functional Validation Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC Power Python
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM GCC
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL microprocessors architecture
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    CPU Power and Performance Validation Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    CPU Python C++
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    Sr. Staff SOC DFT Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT RTL JTAG
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    Senior SoC Analog Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS analog simulation
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL CPU Microprocessors
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL CPU Logic
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    synthesis placement routing
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    Senior SOC DFT Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT BSCAN JTAG
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    SoC FV Functional Validation Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    SoC validation firmware
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    Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM EDA
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Verilog VHDL SystemVerilog
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    CPU Verilog VHDL
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog ASIC GPU
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM OVM
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    Senior CPU Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM Python SystemVerilog
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    GPU SOC Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA silicon
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    Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM ASIC
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM SoC
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Graphics Linux CUDA
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    Atom CPU Layout Design Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI CMOS Unix
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    SoC Power and Performance Validation Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    OSPM Scripting Power-Performance
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    SoC Power and Performance Validation Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC OSPM scripting
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Graphics Drivers APIs
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Graphics Compiler Linux
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Graphics Compilers Linux
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU Linux Compiler
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Linux Vulkan
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    CPU Circuit Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS digital VLSI
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM Clang
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    SOC Design Engineer hot job

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    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    RTL Python Linux
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Microarchitecture
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    Sr. Compiler Engineer/Architect hot job

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    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    compiler LLVM C++
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    Verification SystemVerilog Testbench
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog UVM OVM
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
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    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification SystemVerilog OVM
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
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    C++ LLVM Compiler
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    Senior Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM optimization
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ LLVM GPU
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification SystemVerilog UVM
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    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM VIP
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM OpenMP
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    LLVM C++ Fortran
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM parallel
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Fortran LLVM C++
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    LLVM C C++
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    Compiler Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    compiler LLVM GPU
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM ASIC
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM OpenMP
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    GPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Python
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    GPU Physical Design Engineer Lead hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    ASIC VLSI SoC
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    CPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification UVM Python
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    Design Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog ASIC
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    SoC PnP Validation Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC validation scripting
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    ASIC/FPGA Design Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog FPGA
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    SoC Functional Validation Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC validation FPGA
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    SoC Design Verification Engineer - Emulation hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog RTL emulation
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    Lead SoC Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SoC JTAG
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    SoC Functional Validation Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC PVT scripting
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    CPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL Verilog System
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
    View details
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
    View details
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    E-Core CPU Design Automation Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    EDA STA TCL
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    logic RTL GPU
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    CPU Core Timing and Automation Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    TCL Python AI
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    Senior SoC Physical Design Timing Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    STA Primetime TCL
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    Experienced CPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SystemVerilog high-speed
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    GPU AI Kernel Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ PyTorch SYCL
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM ASIC
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    Senior SoC Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL JTAG Microarchitecture
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    SOC Emulation Validation Engineer

    @ Intel

    ๐Ÿ“Kulim, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    emulation RTL validation
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    SOC Emulation Validation Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL emulation
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    Lead Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    interconnects cache memory
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware Validation Debugging
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware Debugging Validation
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ DirectX Vulkan
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    CPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ part-time
    UVM Specman verification
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    Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog RTL
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL Verilog
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    Triton Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Python LLVM
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    Senior GPU Validation Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU validation SystemVerilog
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“San Francisco, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Microarchitecture
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    SOC Design Engineer hot job

    @ Intel

    ๐Ÿ“San Jose, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog SoC
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    SOC Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Microarchitecture
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Microarchitecture
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Microarchitecture
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Microarchitecture
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    GPU SOC Design Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Microarchitecture
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU C++ Python
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    CPU Physical Design Automation Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI EDA Python
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    CPU Circuit Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    VLSI CMOS circuits
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    CPU Boot Specialist and Debug Tools Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Scripting C C++
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    CPU Circuit Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CMOS digital VLSI
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Firmware x86 Microcontroller
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU C++ Python
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    SoC Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM SoC
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    IP/SOC Verification Engineer/Lead

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM C++
    View details
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    Lead Design Verification Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification UVM SystemVerilog
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    GPU AI Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ PyTorch SYCL
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
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    Verification Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM EDA
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    Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC SoC SystemVerilog
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    Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
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    Senior Design Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SoC
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    Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    ASIC SystemVerilog UVM
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    Senior Verification Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM EDA
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    Triton Compiler Engineering Intern

    @ Intel

    ๐Ÿ“Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š intern
    โฑ๏ธŽ internship
    C++ LLVM MLIR
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    Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
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    GPU/DFT Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT RTL SoC
    View details
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    AI Compiler Engineer

    @ Intel

    ๐Ÿ“San Jose, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    MLIR LLVM Linux
    View details
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    AI Compiler Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    MLIR LLVM C++
    View details
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    Mixed Signal Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL Verilog
    View details
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    Design Verification Methodology/CAD Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    UNIX VCS Python
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ DirectX Vulkan
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    CPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Verilog VHDL SystemVerilog
    View details
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    CPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Verilog VHDL SystemVerilog
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    Senior Design Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
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    Verification Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
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    Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM ASIC
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL SoC Verilog
    View details
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SoC
    View details
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    SoC GFX PnP Validation Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC validation scripting
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    CUDA Linux C++
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    Sr. Linux Kernel Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Linux kernel drivers
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    Lead Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification interconnects UVM
    View details
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    firmware digital algorithm
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    SoC Functional Validation Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    USB4 Thunderbolt Python
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Graphics Validation Debugging
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    Senior Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL Verilog
    View details
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    Senior Verification Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
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    Verification Engineer โ€“ AI SoC Development

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    ASIC SoC SystemVerilog
    View details
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    Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
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    Design Engineer โ€“ AI SoC Development hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SoC
    View details
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    Deep Learning Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Tel Aviv-Yafo, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ MLIR LLVM
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    GPU Physical Design Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Spice SOC Clocking
    View details
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Linux GPU
    View details
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU Vulkan OpenGL
    View details
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    Triton Compiler Engineer

    @ Intel

    ๐Ÿ“Canada, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C++ Python
    View details
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    Sr. Compiler Engineer/Architect hot job

    @ Intel

    ๐Ÿ“Munich, Germany ๐Ÿ‡ฉ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    LLVM C++ GPU
    View details
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    SOC Pre-Silicon Verification Engineer

    @ Intel

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL verification PCIe
    View details
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    SoC Power Thermal Performance Val Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI silicon Python
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    IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog emulation
    View details
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL VHDL Verilog
    View details
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    Senior GPU Software Engineer

    @ Intel

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ DirectX Vulkan
    View details
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    Sr. Compiler Engineer/Architect

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM C++
    View details
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    Sr. Compiler Engineer/Architect hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM GPU
    View details
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C Linux DRM
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    SOC Physical Design Engineer Lead hot job

    @ Intel

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    synthesis routing verification
    View details
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    DFT RTL Design and Integration Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT RTL Scan
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    DFT RTL Design and Integration Engineer hot job

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT RTL scan
    View details
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    SoC Design Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    VLSI RTL DFT
    View details
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    Real-Time Embedded Firmware Verification Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Python VLSI
    View details
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    Firmware Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Firmware C Wireless
    View details
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    SOC Logic Design Engineer

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL Scripting UPF
    View details
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU C++ Python
    View details
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    GPU Software Performance Intern

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š intern
    โฑ๏ธŽ internship
    C++ Python Linux
    View details
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    firmware embedded algorithms
    View details
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    SoC Debug Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Debug SoC Firmware
    View details
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    SoC Debug Engineer

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    debug SoC architecture
    View details
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    SoC Debug Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    debug SoC architecture
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    SoC Debug Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    SoC firmware micro-architecture
    View details
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    SoC Debug Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    SoC debug firmware
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    CPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Python
    View details
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    Compiler Software Engineer

    @ Intel

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ internship
    Compiler LLVM GCC
    View details
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    GPU Compiler Engineer

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ LLVM GPU
    View details
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    CPU Formal Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification SoC abstraction
    View details
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    Senior Physical Design Engineer - CPU Core hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI GDS EDA
    View details
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    SOC Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    UVM SystemVerilog Verification
    View details
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    Triton Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C C++
    View details
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ RTOS ARM
    View details
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    AI Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    MLIR LLVM optimization
    View details
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    AI Compiler Engineer hot job

    @ Intel

    ๐Ÿ“San Jose, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    MLIR LLVM GPU
    View details
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    SOC Analog Integration/Power Delivery Engineer hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Analog Integration Power
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification JasperGold VHDL
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    Physical Design SoC Clock Engineer hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL GDS
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    Graduate Talent

    @ Intel

    ๐Ÿ“Kulim, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ contract
    Python C C++
    View details
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    SOC Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Python C++ Verilog
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    CPU Backend Engineer - Full-Chip Timing hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Timing Analysis Scripting
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Graphics Debug Validation
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    Senior CPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CPU RTL microarchitecture
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    Atom CPU Layout Design Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    VLSI CMOS Unix
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU CUDA DPC++
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    CPU Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Verilog SystemVerilog
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    Linux Kernel Test Development Intern

    @ Intel

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    Linux C Python
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog RTL GPU
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    SOC Design Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog RTL GPU
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    CPU Formal Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification JasperGold SoC
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    Triton Compiler Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Python LLVM
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    Triton Compiler Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Python LLVM
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    AI Compiler and Library Engineer

    @ Intel

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ internship
    C++ Assembly Python
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    SoC PTP Val and Opt Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ contract
    validation automation performance
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    Firmware Integration Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    C++ SystemC Git
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C C++
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    SoC Firmware Architect- Senior Principal Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    firmware architecture FPGAs
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    SoC Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    design GDS synthesis
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    Graduate Talent

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Python C C++
    View details
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    E-core CPU Backend Engineer for Full-Chip Timing

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Timing Static Scripting
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Python RTL
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    GPU Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler optimization LLVM
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    GPU Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ LLVM GPGPU
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU DirectX Vulkan
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFx RTL simulation
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Timing Tcl Perl
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    CPU Backend Engineer - Full-Chip Timing hot job

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Timing STA Scripting
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    GPU Software Development Intern

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š intern
    โฑ๏ธŽ internship
    Python Ansible SQL
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    Boot Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Bootloader BIOS UEFI
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    Senior CPU Circuit Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS digital VLSI
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    CPU Circuit Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    CMOS digital VLSI
    View details
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    Senior Embedded Linux Driver Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Linux C++ Git
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Romania, Romania ๐Ÿ‡ท๐Ÿ‡ด
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification Specman EDA
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    AI Linux Kernel Developer hot job

    @ Intel

    ๐Ÿ“Tel Aviv-Yafo, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Linux Pcie C
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    Senior CPU Circuit Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS VLSI design
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    Senior Logic Design Verification Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog RTOS
    View details
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    Senior IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemC SystemVerilog UVM
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    AI SoC CAD Software Engineer hot job

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Python Git Docker
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    RF Analog Layout Design Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RF Analog Cadence
    View details
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“Phoenix, AZ, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog Python
    View details
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    E-core CPU Backend Engineer for Full-Chip Timing hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Timing STA TCL
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    Triton Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara County, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C++ Python
    View details
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    SoC Physical Design Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Synthesis Routing Verification
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    CPU CAD Design Automation Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verification Python
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    CPU CAD Design Automation Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL VLSI Python
    View details
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    CPU Backend Design Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI P-core Python
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    RTL Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    RTL CPU Logic
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog RTL
    View details
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    Atom CPU Layout Design Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    VLSI CMOS Unix
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    AI SoC CAD Software Engineer

    @ Intel

    ๐Ÿ“Tel Aviv-Yafo, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Python Git EDA
    View details
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFX RTL verification
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    Deep Learning Compiler Engineer

    @ Intel

    ๐Ÿ“Tel Aviv-Yafo, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ LLVM MLIR
    View details
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    RF Analog Layout Design Engineer

    @ Intel

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RF Cadence Mentor
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    GPU SOC Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    design verification verilog
    View details
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    Silicon Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Validation Verification SystemVerilog
    View details
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    Senior Pre-Silicon Design Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verification SystemVerilog OVM
    View details
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    SOC Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    AI Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    MLIR LLVM CUDA
    View details
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    Senior IP Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Boxborough, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification SystemVerilog UVM
    View details
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    SOC Physical Design Engineer Lead

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    design verification synthesis
    View details
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“United States, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
    View details
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    Triton Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C C++
    View details
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ SystemVerilog UVM
    View details
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    SoC Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    design verification synthesis
    View details
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC Debug Verification
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFX RTL scripting
    View details
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    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    UVM SystemVerilog Verification
    View details
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    SOC Design Verification Engineer

    @ Intel

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM Verification
    View details
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    SoC Director

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC Debug Architecture
    View details
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Synthesis Placement CTS
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    SoC Director hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC Architecture Interconnect
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    AI/GPU SoC Lead hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    SoC FPGA RTL
    View details
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL GPU SoC
    View details
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    SoC Functional Post Silicon Validation Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC PCIe USB3
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    GPU Validation Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Validation GPU C++
    View details
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog OVM UVM
    View details
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    CPU Circuit Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    CMOS digital VLSI
    View details
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    Embedded Real-Time Software Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ DevOps Ethernet
    View details
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    GPU SOC Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog GPU
    View details
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU C++ Python
    View details
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    GPU Verification Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification UVM SV
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    synthesis place route
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    GPU Validation Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU Validation Emulation
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    Logic Design Verification Engineer

    @ Intel

    ๐Ÿ“Kulim, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ contract
    SystemVerilog Python Perl
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU firmware driver
    View details
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL architecture microarchitecture
    View details
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    Firmware Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware C C++
    View details
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    CPU Circuit Design Engineer

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    CMOS VLSI digital
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    Mixed Signal Design Verification Engineer hot job

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    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL VLSI SystemVerilog
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    Deep Learning Compiler Engineer

    @ Intel

    ๐Ÿ“Tel Aviv-Yafo, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ MLIR LLVM
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM calibration
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog RTL ASIC
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog RTL
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    CPU Validation Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    validation automation architecture
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    AI Software Solutions Engineer - Embedded

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware RTOS SPI
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    Sr Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM Networking
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    GPU Performance Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU UVM OpenGL
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    GPU Verification Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SV UVM Python
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    GPU compute performance engineer

    @ Intel

    ๐Ÿ“Leixlip, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU AI Python
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    Deep Learning Compiler Engineer

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ MLIR LLVM
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Timing Optimization Synthesis
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Timing Tcl Perl
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    GPU design verification engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification simulation architecture
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    GPU design verification engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification SystemVerilog architecture
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    CPU Verification Engineer/Lead

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verification RTL Specman
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    CPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
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    SoC Logic Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL PCIe
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    SoC Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
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    SoC Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Verilog SystemVerilog
    View details
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    SW Embedded Engineer

    @ Intel

    ๐Ÿ“Tel Aviv-Yafo, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C Yocto Python
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Synthesis Placement CTS
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Design Optimization Synthesis
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    IP Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog Perl OVM
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    GPU Software Optimization Engineer - GPGPU/SYCL

    @ Intel

    ๐Ÿ“United Kingdom, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ SYCL CUDA
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    E-Core Design Verification Engineer

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Verilog UVM FPGA
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    E-Core Senior Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification System Verilog
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    GPU Software Optimization Engineer - GPGPU/SYCL

    @ Intel

    ๐Ÿ“Poland, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU CUDA OpenCL
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    EC firmware development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ RTOS Zephyr
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    Silicon Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Bluetooth C RTOS
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    Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Docker Kubernetes C#
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    GPU Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Python SystemVerilog UVM
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    CPU Power Delivery Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    IR Python Verilog
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    SoC Design Verification Engineer- Power Management

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verification SystemVerilog OVM
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    Compiler Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    compiler LLVM GCC
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    GPU Validation Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU PCIe validation
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification SystemVerilog ASIC
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    Senior Firmware Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C/C++ Coreboot
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    CPU Pre-Si Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    verification debugging simulation
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    CPU Pre-Si Verification Senior Engineer hot job

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VHDL Verilog SystemVerilog
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    Design Verification Engineer

    @ Intel

    ๐Ÿ“Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog UVM TCP-IP
    View details
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    GPU SOC Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog FPGA
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    VLSI Verilog UVM
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    Analog Layout Design Engineer hot job

    @ Intel

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SerDes layout verification
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    SOC DFT Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT RTL SoC
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    GPU Validation Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC validation IP
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    CPU Physical Design Engineer hot job

    @ Intel

    ๐Ÿ“Haifa District, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI TCL Python
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    SOC DFT Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT RTL SCAN
    View details
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Python Diagnostics
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    GPU Software Development Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Linux GPU
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM verification
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    GPU Validation Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU PCIe validation
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    GPU Performance Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU APIs RTL
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    SoC Design Engineer - Manual Debug Team hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    debug validation JTAG
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    SOC DFT Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DFT RTL SCAN
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    Memory Compiler Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SRAM VLSI scripting
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C Linux DRM
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    SOC Pre-Silicon Verification Engineer

    @ Intel

    ๐Ÿ“Ho Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification integration ATE
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC SystemVerilog OVM
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    GPU Logic Design Engineer/PPA Engineer hot job

    @ Intel

    ๐Ÿ“San Diego, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    GPU PPA EDA
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    GPU Logic Design Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL GPU micro-architecture
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    GPU Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog UVM
    View details
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC UVM SystemVerilog
    View details
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM simulation
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    SoC Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog UVM emulation
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    SoC Design Verification Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC verification UVM
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    SoC Verification Engineer hot job

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Verilog SystemVerilog
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    GPU Validation Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    validation emulation FPGA
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    CPU Debug and Verification Engineer

    @ Intel

    ๐Ÿ“Guadalajara, Mexico ๐Ÿ‡ฒ๐Ÿ‡ฝ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Python JTAG
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    GPU Firmware Development Engineer hot job

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    firmware C C++
    View details
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    GPU SOC Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog GPU
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    GPU IP Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog Perl
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    GPU Logic Design Engineer

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Verilog SystemVerilog RTL
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    CPU RTL Design Engineer hot job

    @ Intel

    ๐Ÿ“Austin, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog Timing
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    GPU Design Verification Engineer hot job

    @ Intel

    ๐Ÿ“Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    GPU RTL Verilog
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    SoC Physical Design Engineer

    @ Intel

    ๐Ÿ“Hillsboro, OR, United States of America ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    EDA Synopsys Cadence
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    SOC Verification Engineer- ICE

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ contract
    SOC UVM Verilog
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    GPU Software Development Engineer hot job

    @ Intel

    ๐Ÿ“Gdaล„sk, Poland ๐Ÿ‡ต๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Linux C DRM
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    CPU Circuit Design Engineer/Lead

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CPU SRAM Verilog
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    CPU Physical Design Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Synthesis Placement CTS
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    Silicon Firmware Development Engineer

    @ Intel

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
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Industries
Semiconductor Consumer Electronics Telecommunications Computer Electronics
Company Info
Employees 10001+
Founded 1968
Type Public
Stock INTC
Glassdoor 4.2
Connect
Active Hiring Locations
๐Ÿ“ Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ 10
๐Ÿ“ Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ 5
๐Ÿ“ Phoenix, United States ๐Ÿ‡บ๐Ÿ‡ธ 3
๐Ÿ“ Santa Clara, United States of America ๐Ÿ‡บ๐Ÿ‡ธ 3
๐Ÿ“ Folsom, United States of America ๐Ÿ‡บ๐Ÿ‡ธ 3
Top Roles
RTL Design Engineer (5) SoC Design Engineer (5) CPU Engineer (4) Analog Design Engineer (4) Firmware Engineer (3)
Key Skills
Python SystemVerilog RTL C++ Verilog UVM SoC GPU
Seniority Levels
senior (23) mid-level (8) entry-level (3) junior (1)
Work Arrangement
On-site (35)
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Intel Job Alerts

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About Intel

Intel manufactures microprocessors, chipsets, and integrated circuits, headquartered in Santa Clara, California. Its Core and Xeon processor families serve a wide range of markets, including personal computing, data centers, and AI applications. Engineering disciplines at Intel include hardware design, software development, and systems architecture. Engineers tackle challenges in power efficiency, performance optimization, and integration of advanced technologies like AI and machine learning. With over 110,000 employees and multiple design and manufacturing sites worldwide, Intel is a leader in semiconductor innovation.

Intel Career Opportunities

Intel currently has 35 active embedded systems positions spanning 8 countries. All positions are on-site, typical for hardware-focused roles requiring lab access and equipment. Recognized as a top-tier employer (95.0/100), Intel offers competitive compensation and strong career development paths in embedded engineering.

Intel Hiring Trends

* Data represents job posting activity over the past 6 months: Jan 2026 through Jun 2026

Intel's hiring pace has moderated recently (27 openings this month vs 29 last month), which is common after major hiring pushes or as projects move from development to deployment phases.

Over the past 6 months, Intel averaged 72.2 job postings per month, with peak hiring in Apr 2026 (145 openings). For embedded systems roles, hiring activity typically correlates with product development cycles, especially for firmware teams during pre-production phases and hardware engineers during prototyping.

Current Month
27 jobs

๐Ÿ“‰ -7% change

6-Month Average
72.2 jobs/month

Consistent hiring velocity

Peak Activity
145 jobs

Apr 2026

Required Skills at Intel

Python is the most in-demand skill at Intel, appearing in 29% of all job listings (past and present). This skill is important but not universal, indicating diverse technical needs across different product lines or teams.

Intel's technology stack spans 389 distinct skills and tools, reflecting the multifaceted nature of embedded systems development. The broad technical diversity (389 technologies) suggests work on complex, multi-domain projects requiring both hardware and software expertise.

Python
29% of roles
29%
SystemVerilog
29% of roles
29%
RTL
24% of roles
24%
C++
23% of roles
23%
Verilog
20% of roles
20%
UVM
20% of roles
20%
SoC
18% of roles
18%
GPU
14% of roles
14%
verification
12% of roles
12%
LLVM
11% of roles
11%
Linux
9% of roles
9%
EDA
9% of roles
9%

Engineers joining Intel should combine depth in key areas with adaptability. The mix of hardware skills (PCB design, schematics) and firmware expertise (RTOS, embedded C) indicates full-stack embedded development where engineers work across the hardware-software boundary. Candidates with adjacent skills (version control, testing frameworks, communication protocols) typically advance faster by contributing across the development lifecycle.

Engineering Roles at Intel

Intel's primary hiring focus is RTL Design Engineer with 5 open positions. High-volume recruitment for a single role type typically indicates either a growing team building similar capabilities or a newly formed department scaling rapidly.

Multiple openings in the same discipline create advantages for new hires: stronger peer support networks, established onboarding processes, and clearer career progression paths as the team matures. Engineers often find collaborative environments more conducive to professional growth.

RTL Design Engineer
5 positions (14%)
5
SoC Design Engineer
5 positions (14%)
5
CPU Engineer
4 positions (11%)
4
Analog Design Engineer
4 positions (11%)
4
Firmware Engineer
3 positions (9%)
3
Embedded Software Engineer
3 positions (9%)
3
Hardware Engineer
2 positions (6%)
2
Electrical Engineer
2 positions (6%)
2
ASIC Design Engineer
1 position (3%)
1

Experience level distribution: 66% of openings target senior-level engineers. The range across 4 experience levels suggests a well-balanced team structure with opportunities for both experienced engineers and those earlier in their careers.

Where Intel is Hiring

Intel operates across 16 countries with 53 total hiring locations. Multi-geography recruitment typically indicates either distributed engineering teams, expansion into new markets, or proximity to manufacturing and customer operations.

Bengaluru, India serves as a primary hiring hub with 20% of all roles (133 positions). Engineering capabilities are distributed relatively evenly across locations, suggesting a genuinely multi-site development model rather than a single headquarters-centric approach.

๐Ÿ‡ฎ๐Ÿ‡ณ
Bengaluru, India
10 active jobs
10
๐Ÿ‡ฎ๐Ÿ‡ฑ
Petah Tikva, Israel
5 active jobs
5
๐Ÿ‡บ๐Ÿ‡ธ
Phoenix, United States
3 active jobs
3
๐Ÿ‡บ๐Ÿ‡ธ
Santa Clara, United States of America
3 active jobs
3
๐Ÿ‡บ๐Ÿ‡ธ
Folsom, United States of America
3 active jobs
3
๐Ÿ‡บ๐Ÿ‡ธ
Hillsboro, United States of America
3 active jobs
3
๐Ÿ‡บ๐Ÿ‡ธ
Chandler, United States
2 active jobs
2
๐Ÿ‡จ๐Ÿ‡ฆ
Ottawa, Canada
1 active job
1
๐Ÿ‡ฉ๐Ÿ‡ช
Munich, Germany
1 active job
1
๐Ÿ‡บ๐Ÿ‡ธ
Chandler, United States of America
1 active job
1
๐Ÿ‡ฒ๐Ÿ‡พ
Kulim, Malaysia
1 active job
1
๐Ÿ‡ฎ๐Ÿ‡ฑ
Haifa, Israel
1 active job
1
๐Ÿ‡น๐Ÿ‡ผ
Hsinchu, Taiwan
1 active job
1
๐Ÿ‡บ๐Ÿ‡ธ
Austin, United States of America
70 previous jobs
๐Ÿ“
Hillsboro, OR
69 previous jobs
๐Ÿ‡ฒ๐Ÿ‡ฝ
Guadalajara, Mexico
25 previous jobs
๐Ÿ‡ฒ๐Ÿ‡พ
Taman Pulau Pinang, Malaysia
22 previous jobs
๐Ÿ‡ฎ๐Ÿ‡ฑ
Haifa District, Israel
19 previous jobs
๐Ÿ“
Phoenix, AZ
19 previous jobs

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