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Synopsys Inc

Design Verification, Sr Staff Engineer in HCMC

๐Ÿ“ŒHo Chi Minh City, Vietnam ๐Ÿ‡ป๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification. You thrive in a collaborative environment and have a keen eye for detail. Your technical expertise is complemented by your ability to communicate effectively and work well within a team. You are self-motivated and enthusiastic about technology and problem-solving. With a minimum of 5 years of experience in design verification, you have honed your skills in using simulation tools, scripting languages, and advanced verification techniques. You have a solid understanding of digital and mixed-signal designs and are eager to contribute to cutting-edge technologies that enable Data Center, AI/ML, and 5G applications.

What Youโ€™ll Be Doing:

  • Working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP.
  • Planning tests, checklists, coverage, and assertion planning.
  • Creating detailed verification environments from functional specifications.
  • Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
  • Writing test cases, checkers, and coverage that implement the verification test plan.
  • Debugging simulations, including those of real signals modeled using SystemVerilog for analog.
  • Performing RTL, GLS, and co-simulations and ensuring coverage closure.
  • Participating in technical reviews and contributing actively.
  • Providing customer support with the bring-up of IP in customer simulation environments.
  • Following and improving development processes to ensure high-quality output.

The Impact You Will Have:

  • Contributing to the development and validation of high-performance digital and mixed-signal IP.
  • Ensuring the successful implementation of verification test plans.
  • Enhancing the reliability and performance of our products through meticulous debugging and testing.
  • Supporting customers in integrating our IP into their systems, ensuring seamless operation.
  • Improving development processes to enhance efficiency and output quality.
  • Collaborating with a global team of experts, driving innovation and technological advancements.

What Youโ€™ll Need:

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 8+ years of experience in design verification.
  • Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).
  • Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.
  • Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

Who You Are:

  • Highly responsible and result-oriented.
  • Excellent English communication skills, both verbal and written.
  • A great team player, willing to support others.
  • Self-motivated and highly enthusiastic about technology and solving problems.

The Team Youโ€™ll Be A Part Of:

You will join a highly motivated and talented engineering team in Vietnam, working alongside experts from around the world. The team is dedicated to developing and validating complex digital and mixed-signal IP, driving innovation in Data Center, AI/ML, and 5G applications.
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