Soc Design Verification Engineer

Company Description Sivaltech is an established ASIC/FPGA, analog, and embedded software design services company with offices in California, USA and Bangalore, India. The company is a preferred design services partner for Fortune 500 organizations as well as startups in the semiconductor industry. With expertise across domains such as GPUs, CPUs, wireless, communications, medical, broadband, and consumer electronics, Sivaltech supports clients in addressing complex design challenges. Team members collaborate on advanced technologies and gain exposure to diverse, high-impact projects. The work environment emphasizes technical excellence, problem-solving, and long-term client partnerships.
Role Description The Design Verification Engineer is responsible for ensuring the functional correctness and quality of complex ASIC/FPGA designs in a full-time, on-site role based in the San Francisco Bay Area. Day-to-day tasks include developing and executing verification plans, creating testbenches, writing and reviewing verification environments, and performing functional and formal verification of RTL designs. The role involves debugging design and testbench issues, analyzing coverage metrics, and driving closure of verification gaps in collaboration with design and architecture teams. The engineer will work closely with cross-functional stakeholders to review specifications, refine requirements, and contribute to continuous improvement of verification methodologies and flows. Participation in design reviews, documentation of verification results, and support for tapeout and post-silicon bring-up may also be part of the responsibilities.
Qualifications

• Candidates should possess strong skills in Functional Verification, including testbench development, simulation, and coverage analysis.
• Candidates should possess skills in Formal Verification techniques and tools to complement simulation-based methodologies.
• Candidates should possess solid RTL Design skills and familiarity with hardware description languages such as Verilog or SystemVerilog.
• Candidates should possess a strong foundation in Computer Architecture, including pipelines, caches, memory subsystems, and bus protocols.
• Candidates should possess excellent Debugging skills for identifying, analyzing, and resolving design and verification issues.
• Strong understanding of verification methodologies (e.g., UVM or similar), scripting languages (such as Python, Perl, or Shell), and version control tools is beneficial.
• Effective communication, collaboration, and documentation skills, with the ability to work in cross-functional engineering teams, are required.
• A bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field, along with prior experience in semiconductor design or verification, is preferred.