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Cadence

Cadence

Accelerating electronic design with innovative software and engineering solutions.

๐Ÿ“ San Jose, California

7 Open Positions
4 Active Locations
Posted

About Cadence

Cadence develops electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries, headquartered in San Jose, California. Its flagship products include the Allegro platform for PCB design and the Virtuoso platform for custom IC design, serving markets from consumer electronics to automotive and telecommunications. Engineering disciplines at Cadence encompass digital and analog design, verification, and system-level design. Engineers tackle challenges in signal integrity, power management, and design for manufacturability. With a global presence and a workforce of over 8,000 employees, Cadence is a key player in the EDA market, continuously evolving its tools to meet the demands of advanced semiconductor technologies.

Current Job Openings

7 jobs

All Cadence Job Openings

  • Cadence logo

    Sr Principal AE in PCB

    @ Cadence

    ๐Ÿ“Milan, Italy ๐Ÿ‡ฎ๐Ÿ‡น
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCB Allegro Sigrity
    View Sr Principal AE in PCB
  • Cadence logo

    Application Engineering Director - IC Design Verification hot job

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog Verilog UVM
    View Application Engineering Director - IC Design Verification
  • Cadence logo

    Junior Application Engineer

    @ Cadence

    ๐Ÿ“Paris, France ๐Ÿ‡ซ๐Ÿ‡ท
    ๐Ÿ“Š junior
    โฑ๏ธŽ full-time
    PCB simulation TCL
    View Junior Application Engineer
  • Cadence logo

    Lead Firmware Engineer

    @ Cadence

    ๐Ÿ“Beijing, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    DDR5 C Verilog
    View Lead Firmware Engineer
  • Cadence logo

    Lead Firmware Engineer

    @ Cadence

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    firmware microcontroller DDR5
    View Lead Firmware Engineer
  • Cadence logo

    Firmware Engineer II

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    DDR5 firmware microcontroller
    View Firmware Engineer II
  • Cadence logo

    Sr Principal Application Engineer โ€“ Allegro PCB Design Tools hot job

    @ Cadence

    ๐Ÿ“Home Place, IN, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCB RF Allegro
    View Sr Principal Application Engineer โ€“ Allegro PCB Design Tools
  • Previously posted positions that may provide insight into Cadence's hiring patterns

  • Expired
    Cadence logo

    Lead Software Engineer - Compiler/LLVM

    @ Cadence

    ๐Ÿ“Cork, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    LLVM C++ DSP
    View details
    View Lead Software Engineer - Compiler/LLVM
  • Expired
    Cadence logo

    Software Engineer II: AI Compiler Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Compiler LLVM MLIR
    View details
    View Software Engineer II: AI Compiler Engineer
  • Expired
    Cadence logo

    Software Engineer II: AI Compiler Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC LLVM MLIR
    View details
    View Software Engineer II: AI Compiler Engineer
  • Expired
    Cadence logo

    Senior Principal Asic Verification Engineer

    @ Cadence

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification interconnects AMBA
    View details
    View Senior Principal Asic Verification Engineer
  • Expired
    Cadence logo

    Software Engineer II : AI Compiler Engineer

    @ Cadence

    ๐Ÿ“Belo Horizonte, Brazil ๐Ÿ‡ง๐Ÿ‡ท
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    AI Compiler TensorFlow
    View details
    View Software Engineer II : AI Compiler Engineer
  • Expired
    Cadence logo

    Sr Embedded Software engineer

    @ Cadence

    ๐Ÿ“Cork, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C Python Linux
    View details
    View Sr Embedded Software engineer
  • Expired
    Cadence logo

    Software Engineer II - Compiler/LLVM

    @ Cadence

    ๐Ÿ“Belo Horizonte, Brazil ๐Ÿ‡ง๐Ÿ‡ท
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C C++ LLVM
    View details
    View Software Engineer II - Compiler/LLVM
  • Expired
    Cadence logo

    Software Engineer II - Compiler/LLVM

    @ Cadence

    ๐Ÿ“Cork, Ireland ๐Ÿ‡ฎ๐Ÿ‡ช
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C C++ LLVM
    View details
    View Software Engineer II - Compiler/LLVM
  • Expired
    Cadence logo

    Principal Firmware Engineer

    @ Cadence

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    C++ Python DSP
    View details
    View Principal Firmware Engineer
  • Expired
    Cadence logo

    Principal Application Engineer โ€“ Allegro PCB Design Tools hot job

    @ Cadence

    ๐Ÿ“Ontario, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    PCB Allegro RF
    View details
    View Principal Application Engineer โ€“ Allegro PCB Design Tools
  • Expired
    Cadence logo

    Quantum Product Engineer

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    quantum Virtuoso Spectre
    View details
    View Quantum Product Engineer
  • Expired
    Cadence logo

    Senior Principal Software Engineer - Compiler Development hot job

    @ Cadence

    ๐Ÿ“Burlington, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Compiler SystemVerilog C++
    View details
    View Senior Principal Software Engineer - Compiler Development
  • Expired
    Cadence logo

    ASIC Verification, Account Technical Executive

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification Xcelium Jasper
    View details
    View ASIC Verification, Account Technical Executive
  • Expired
    Cadence logo

    Principal Product Engineer

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal Virtuoso
    View details
    View Principal Product Engineer
  • Expired
    Cadence logo

    Principal Product Engineer hot job

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    analog mixed-signal automation
    View details
    View Principal Product Engineer
  • Expired
    Cadence logo

    Lead Hardware Engineer - DFT IP R&D hot job

    @ Cadence

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog DFT
    View details
    View Lead Hardware Engineer - DFT IP R&D
  • Expired
    Cadence logo

    Lead Hardware Engineer - DFT IP R&D

    @ Cadence

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View Lead Hardware Engineer - DFT IP R&D
  • Expired
    Cadence logo

    Senior Principal RTL Design Engineer hot job

    @ Cadence

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View Senior Principal RTL Design Engineer
  • Expired
    Cadence logo

    Lead Application Engineer โ€“ Custom IC Design and Implementation

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    simulation layout electromagnetic
    View details
    View Lead Application Engineer โ€“ Custom IC Design and Implementation
  • Expired
    Cadence logo

    Application Engineer I: Analog IC Design and Layout

    @ Cadence

    ๐Ÿ“Belo Horizonte, Brazil ๐Ÿ‡ง๐Ÿ‡ท
    ๐Ÿ“Š entry-level
    โฑ๏ธŽ full-time
    Analog CMOS Spectre
    View details
    View Application Engineer I: Analog IC Design and Layout
  • Expired
    Cadence logo

    Lead Firmware Engineer

    @ Cadence

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ Python SERDES
    View details
    View Lead Firmware Engineer
  • Expired
    Cadence logo

    Principal Analog IC Design Engineer, High Speed SerDes hot job

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SerDes PLL ADC
    View details
    View Principal Analog IC Design Engineer, High Speed SerDes
  • Expired
    Cadence logo

    Senior Principal Software Engineer - Compiler Development

    @ Cadence

    ๐Ÿ“Burlington, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ SystemVerilog LLVM
    View details
    View Senior Principal Software Engineer - Compiler Development
  • Expired
    Cadence logo

    DSP or Serdes RTL Sr Principal Digital Design Engineer hot job

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    DSP SerDes RTL
    View details
    View DSP or Serdes RTL Sr Principal Digital Design Engineer
  • Expired
    Cadence logo

    Senior Principal IC Design Verification Application Engineer hot job

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog VHDL Verilog
    View details
    View Senior Principal IC Design Verification Application Engineer
  • Expired
    Cadence logo

    Firmware Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    Firmware Microcontrollers DDR5
    View details
    View Firmware Engineer
  • Expired
    Cadence logo

    Sr Account Technical Executive - ASIC/SoC

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification Xcelium Jasper
    View details
    View Sr Account Technical Executive - ASIC/SoC
  • Expired
    Cadence logo

    ASIC Verification, Account Technical Executive

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verification Xcelium Jasper
    View details
    View ASIC Verification, Account Technical Executive
  • Expired
    Cadence logo

    Principal Firmware Engineer hot job

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    SerDes ADC DAC
    View details
    View Principal Firmware Engineer
  • Expired
    Cadence logo

    Lead Firmware Engineer

    @ Cadence

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ Python SERDES
    View details
    View Lead Firmware Engineer
  • Expired
    Cadence logo

    IC Design Verification Application Engineer

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SystemVerilog VHDL Verilog
    View details
    View IC Design Verification Application Engineer
  • Expired
    Cadence logo

    Principal Design Verification DDR Engineer

    @ Cadence

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog verification
    View details
    View Principal Design Verification DDR Engineer
  • Expired
    Cadence logo

    Lead Mixed Signal Design Verification Engineer

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification analog mixed-signal
    View details
    View Lead Mixed Signal Design Verification Engineer
  • Expired
    Cadence logo

    Quantum Intern

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    superconducting Qiskit transmons
    View details
    View Quantum Intern
  • Expired
    Cadence logo

    Principal Firmware Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    firmware microcontroller debugging
    View details
    View Principal Firmware Engineer
  • Expired
    Cadence logo

    Lead Mixed Signal Design Verification Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification modeling simulation
    View details
    View Lead Mixed Signal Design Verification Engineer
  • Expired
    Cadence logo

    Lead Mixed Signal Design Verification Engineer

    @ Cadence

    ๐Ÿ“Cary, NC, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    mixed-signal verification modeling
    View details
    View Lead Mixed Signal Design Verification Engineer
  • Expired
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    Design Verification Lead Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    VLSI UVM SystemVerilog
    View details
    View Design Verification Lead Engineer
  • Expired
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    Analog Design Engineer II

    @ Cadence

    ๐Ÿ“Nanjing, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SerDes AMS Cadence
    View details
    View Analog Design Engineer II
  • Expired
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    Design Engineer II: Digital Design Verification

    @ Cadence

    ๐Ÿ“Greater Campinas, Brazil ๐Ÿ‡ง๐Ÿ‡ท
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    System-Verilog UVM C/C++
    View details
    View Design Engineer II: Digital Design Verification
  • Expired
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    Lead Analog Design Engineer

    @ Cadence

    ๐Ÿ“Nanjing, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    CMOS SerDes PLLs
    View details
    View Lead Analog Design Engineer
  • Expired
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    Core RTL design engineeer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL specification validation
    View details
    View Core RTL design engineeer
  • Expired
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    Design Engineer II

    @ Cadence

    ๐Ÿ“Edinburgh, United Kingdom ๐Ÿ‡ฌ๐Ÿ‡ง
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog FPGA
    View details
    View Design Engineer II
  • Expired
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    Software Engineer II - Firmware

    @ Cadence

    ๐Ÿ“Nanjing, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    USB UCIe PCIe
    View details
    View Software Engineer II - Firmware
  • Expired
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    Senior IC Design Verification Application Engineer hot job

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemVerilog VHDL Verilog
    View details
    View Senior IC Design Verification Application Engineer
  • Expired
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    Principal Analog Design Engineer hot job

    @ Cadence

    ๐Ÿ“Nanjing, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    CMOS SerDes Cadence
    View details
    View Principal Analog Design Engineer
  • Expired
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    Principal Analog Design Engineer

    @ Cadence

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    CMOS SerDes simulation
    View details
    View Principal Analog Design Engineer
  • Expired
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    Lead Firmware Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    firmware microcontroller DDR5
    View details
    View Lead Firmware Engineer
  • Expired
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    Lead Application Engineer-Analog Design

    @ Cadence

    ๐Ÿ“Yokohama, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SPICE Verilog-A Python
    View details
    View Lead Application Engineer-Analog Design
  • Expired
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    Lead Firmware Engineer

    @ Cadence

    ๐Ÿ“Austin, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Firmware C DDR5
    View details
    View Lead Firmware Engineer
  • Expired
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    Custom Layout Designer

    @ Cadence

    ๐Ÿ“Cary, NC, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    layout analog CMOS
    View details
    View Custom Layout Designer
  • Expired
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    Principal FPGA Design Engineer hot job

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog Xilinx
    View details
    View Principal FPGA Design Engineer
  • Expired
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    SoC Modeling Architect hot job

    @ Cadence

    ๐Ÿ“California, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ SystemC TLM
    View details
    View SoC Modeling Architect
  • Expired
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    Principal Design Engineer - Analog Design

    @ Cadence

    ๐Ÿ“Toronto, Canada ๐Ÿ‡จ๐Ÿ‡ฆ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes jitter PLL
    View details
    View Principal Design Engineer - Analog Design
  • Expired
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    Sr Principal RTL Design Engineer

    @ Cadence

    ๐Ÿ“Bengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog UCIe PCIe
    View details
    View Sr Principal RTL Design Engineer
  • Expired
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    Principal Product Engineer - RTL Design

    @ Cadence

    ๐Ÿ“Noida, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    RTL SystemVerilog SDC
    View details
    View Principal Product Engineer - RTL Design
  • Expired
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    Lead Analog Design Engineer

    @ Cadence

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š lead
    โฑ๏ธŽ full-time
    Analog PLL Circuit
    View details
    View Lead Analog Design Engineer
  • Expired
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    Application Engineer for PCB Design

    @ Cadence

    ๐Ÿ“Petah Tikva, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    PCB Cadence Allegro
    View details
    View Application Engineer for PCB Design
  • Expired
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    Principal FPGA Design Engineer

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog Xilinx
    View details
    View Principal FPGA Design Engineer
  • Expired
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    Principal FPGA Design Engineer

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog Vivado
    View details
    View Principal FPGA Design Engineer
  • Expired
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    DSP or Serdes RTL Lead Digital Design Engineer

    @ Cadence

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    DSP SerDes Verilog
    View details
    View DSP or Serdes RTL Lead Digital Design Engineer
  • Expired
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    Lead Application Engineer - Design Verification

    @ Cadence

    ๐Ÿ“Yokohama, Japan ๐Ÿ‡ฏ๐Ÿ‡ต
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog VHDL SystemVerilog
    View details
    View Lead Application Engineer - Design Verification
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Company Info
Employees 10001+
Founded 1988
Type Public
Stock CDNS
Glassdoor 4.2
Connect
Active Hiring Locations
๐Ÿ“ Milan, Italy ๐Ÿ‡ฎ๐Ÿ‡น 1
๐Ÿ“ San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ 1
๐Ÿ“ Paris, France ๐Ÿ‡ซ๐Ÿ‡ท 1
๐Ÿ“ Beijing, China ๐Ÿ‡จ๐Ÿ‡ณ 1
๐Ÿ“ Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ 1
Top Roles
Embedded Systems Engineer (3) Firmware Engineer (3) Design Verification Engineer (1)
Key Skills
Verilog SystemVerilog verification UVM Python SerDes RTL LLVM
Seniority Levels
senior (3) lead (2) junior (1) mid-level (1)
Work Arrangement
On-site (7)

About Cadence

Cadence develops electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries, headquartered in San Jose, California. Its flagship products include the Allegro platform for PCB design and the Virtuoso platform for custom IC design, serving markets from consumer electronics to automotive and telecommunications. Engineering disciplines at Cadence encompass digital and analog design, verification, and system-level design. Engineers tackle challenges in signal integrity, power management, and design for manufacturability. With a global presence and a workforce of over 8,000 employees, Cadence is a key player in the EDA market, continuously evolving its tools to meet the demands of advanced semiconductor technologies.

Cadence Career Opportunities

Cadence currently has 7 active embedded systems positions spanning 4 countries. All positions are on-site, typical for hardware-focused roles requiring lab access and equipment. Cadence (rating: 40.0/100) actively recruits embedded talent for product development and engineering roles.

Cadence Hiring Trends

* Data represents job posting activity over the past 6 months: Jan 2026 through Jun 2026

Cadence's hiring pace has moderated recently (13 openings this month vs 15 last month), which is common after major hiring pushes or as projects move from development to deployment phases.

Over the past 6 months, Cadence averaged 8.3 job postings per month, with peak hiring in May 2026 (15 openings). For embedded systems roles, hiring activity typically correlates with product development cycles, especially for firmware teams during pre-production phases and hardware engineers during prototyping.

Current Month
13 jobs

๐Ÿ“‰ -13% change

6-Month Average
8.3 jobs/month

Consistent hiring velocity

Peak Activity
15 jobs

May 2026

Required Skills at Cadence

Verilog is the most in-demand skill at Cadence, appearing in 23% of all job listings (past and present). This skill is important but not universal, indicating diverse technical needs across different product lines or teams.

Cadence's technology stack spans 125 distinct skills and tools, reflecting the multifaceted nature of embedded systems development. The broad technical diversity (125 technologies) suggests work on complex, multi-domain projects requiring both hardware and software expertise.

Verilog
23% of roles
23%
SystemVerilog
20% of roles
20%
verification
16% of roles
16%
UVM
13% of roles
13%
Python
13% of roles
13%
SerDes
13% of roles
13%
RTL
12% of roles
12%
LLVM
12% of roles
12%
C++
12% of roles
12%
DSP
12% of roles
12%
C
10% of roles
10%
simulation
9% of roles
9%

Engineers joining Cadence should combine depth in key areas with adaptability. The mix of hardware skills (PCB design, schematics) and firmware expertise (RTOS, embedded C) indicates full-stack embedded development where engineers work across the hardware-software boundary. Candidates with adjacent skills (version control, testing frameworks, communication protocols) typically advance faster by contributing across the development lifecycle.

Engineering Roles at Cadence

Cadence's primary hiring focus is Embedded Systems Engineer with 3 open positions. High-volume recruitment for a single role type typically indicates either a growing team building similar capabilities or a newly formed department scaling rapidly.

Multiple openings in the same discipline create advantages for new hires: stronger peer support networks, established onboarding processes, and clearer career progression paths as the team matures. Engineers often find collaborative environments more conducive to professional growth.

Embedded Systems Engineer
3 positions (43%)
3
Firmware Engineer
3 positions (43%)
3
Design Verification Engineer
1 position (14%)
1

Experience level distribution: 43% of openings target senior-level engineers. The range across 4 experience levels suggests a well-balanced team structure with opportunities for both experienced engineers and those earlier in their careers.

Where Cadence is Hiring

Cadence operates across 11 countries with 22 total hiring locations. Multi-geography recruitment typically indicates either distributed engineering teams, expansion into new markets, or proximity to manufacturing and customer operations.

San Jose, United States serves as a primary hiring hub with 28% of all roles (19 positions). Engineering capabilities are distributed relatively evenly across locations, suggesting a genuinely multi-site development model rather than a single headquarters-centric approach.

๐Ÿ‡ฎ๐Ÿ‡น
Milan, Italy
1 active job
1
๐Ÿ‡บ๐Ÿ‡ธ
San Jose, United States
1 active job
1
๐Ÿ‡ซ๐Ÿ‡ท
Paris, France
1 active job
1
๐Ÿ‡จ๐Ÿ‡ณ
Beijing, China
1 active job
1
๐Ÿ‡จ๐Ÿ‡ณ
Shanghai, China
1 active job
1
๐Ÿ‡บ๐Ÿ‡ธ
Austin, United States
1 active job
1
๐Ÿ“
Home Place, IN
1 active job
1
๐Ÿ‡ฎ๐Ÿ‡ณ
Bengaluru, India
6 previous jobs
๐Ÿ‡จ๐Ÿ‡ณ
Nanjing, China
4 previous jobs
๐Ÿ‡ฎ๐Ÿ‡ช
Cork, Ireland
3 previous jobs
๐Ÿ‡ฎ๐Ÿ‡ณ
Noida, India
3 previous jobs
๐Ÿ‡ง๐Ÿ‡ท
Belo Horizonte, Brazil
3 previous jobs
๐Ÿ‡บ๐Ÿ‡ธ
Burlington, United States
2 previous jobs

Companies Similar to Cadence

These employers share technical focus areas with Cadence and are actively hiring embedded engineers. Exploring multiple companies helps candidates understand market compensation, compare technical challenges, and identify the best cultural and technical fit for their career goals.

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Verkada

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๐Ÿ’ผ 34 openings
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Shield AI

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SiMa.ai

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๐Ÿ’ผ 12 openings
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Microsoft logo

Microsoft

๐Ÿ“Redmond, Washington
๐Ÿ’ผ 378 openings
๐Ÿ‘ฅ 10001+
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Applied Intuition logo

Applied Intuition

๐Ÿ“Sunnyvale, California
๐Ÿ’ผ 59 openings
๐Ÿ‘ฅ 1001-5000
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Pony.ai logo

Pony.ai

๐Ÿ“Fremont, California
๐Ÿ’ผ 2 openings
๐Ÿ‘ฅ 1001-5000
Software Development

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