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Cadence

Lead Application Engineer - Design Verification

๐Ÿ“ŒYokohama, Japan ๐Ÿ‡ฏ๐Ÿ‡ต

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibility

  • Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
  • Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
  • Train, ramp-up and accompany customer project.
  • Conduct basic and advanced trainings, presentations and demos as necessary.
  • Providing technical expertise to address clientsโ€™ queries, which need expert involvement.
  • Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Job Requirements

4-6 or above yearsโ€™ experience in the following areas:

  • Design experience in Verilog/VHDL for IP or SoC chip level.
  • Verification with knowledge of System Verilog/VHDL and HDL simulators.
  • Experience of using formal verification, JasperGold experience is a plus.
  • Experience with hardware emulator or accelerator is a big advantage.
  • Advanced Verification Methodology like UVM is a plus.
  • Strong verbal and written communication skills in Japanese is needed.
  • Business-level English proficiency is preferred.
  • Strong teamwork skills with good human relationship.

Weโ€™re doing work that matters. Help us solve what others canโ€™t.
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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

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