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Cadence

Lead Application Engineer-Analog Design

๐Ÿ“ŒYokohama, Japan ๐Ÿ‡ฏ๐Ÿ‡ต

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Customer support/consulting based on Virtuoso platform, Cadence's A/MS IC design environment.
  • Main product๏ผšVirtuoso Schematic Editor (VSE), Spectre Circuit Simulator
  • https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design/circuit-design.html
  • Qualification Requirements
  • Majored in Electrical Engineering or some other equivalent
  • Has the knowledge and desire to take on new challenges
  • Experiences/Skills
  • At least 5 years of experience for A/MS IC circuit design and knowledge.
  • Having experiences of SPICE simulation / mixed-signal simulation.
  • Having experiences of signal integrity/power integrity analysis.
  • Having experiences of electromigration / IR drop analysis.
  • Having experiences of design rule/LVS(Layout vs Schematic)/parasitic extraction.
  • Having knowledge and experience of thermal analysis for IC design/PCB/package.
  • Programing experiences, such as Perl, Tcl, Python, SKILL etc.
  • Good organization and communication skills between difference groups and customers.
  • Communication skill and technical conversation in English.
  • Must have Japanese communication skill. English or Chinese is a plus.
  • Verilog-A/Verilog-AMS/System Verilog Real modeling experience is a plus.
  • Knowledge of 16nm (or beyond) process desirable.
  • Over 3 years of experience for A/MS design or product support as CAD engineer. Experiences on Virtuoso or Spectre desirable

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