In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits in the latest FinFET process nodes. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team

Experience in design of Charge-pump PLLs, Fractional-N PLLs, DLL design techniques, LDO design techniques

Hands-on experience on designing charge pumps, LC VCOs, Ring oscillators, phase interpolator, bandgap reference, etc.

In depth familiarity with transistor level circuit design at SPICE netlist level and should be capable to develop SPICE verification testbench

Design exposure in advanced process nodes (FinFETs)

Hands on experience with industry standard tools (Cadence, Synopsys, Mentor) for schematic capture spice simulations.

Familiarity with automation / Scripting language (TCL, Python, PERL).

Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of device mismatch and proximity effects.

understanding of ESD issues and reliability issues

Looking for 1-2 years of experience in Analog design with master's degree or 2-4 years of experience in in Analog design with bachelor's degree

In depth familiarity with transistor level circuit design - sound CMOS design fundamentals.

Silicon-proven experience implementing circuits for the PLL within Highspeed SerDes