ASIC Digital Design, Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of digital design where the difference between RTL that synthesizes cleanly and RTL that becomes someone else's nightmare is a decision you made on Tuesday. You know that writing Verilog is the easy part. The hard part is writing Verilog that closes timing, passes CDC without waivers, and does not make the implementation team want to rewrite your entire block.

You think about synthesis while you write RTL. Timing arcs are not abstract concepts, they are the reason you structured that state machine the way you did. When a design review surfaces a potential CDC issue, you are already three steps ahead, sketching the synchronizer and thinking through the corner cases. At Synopsys, you will work on real IP that ships in real products.

What You'll Be Doing

• Design and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog.
• Refine micro-architecture with focus on synthesizability, timing, testability, area, and power tradeoffs.
• Drive synthesis and front-end implementation activities.
• Support CDC/RDC/Lint signoff readiness and collaborate on design-quality closure.
• Work with implementation teams on STA fundamentals, timing constraints, and timing arc understanding.
• Collaborate with verification teams on functional debug, test planning, assertions, and coverage.
• Support debug and issue resolution using Verdi or similar debug tools.
• Participate in design reviews and help resolve integration and interoperability issues across product lines.
• Develop automation scripts for design, debug, reporting, and productivity.
  
  

The Impact You Will Have

• Your RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwide
• You will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designs
• Your collaboration will catch issues earlier, reducing costly respins and late-stage fixes
• The automation you build will improve design productivity across multiple product lines
• Your attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff risk
  
  

What You'll Need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of experience in digital design and/or RTL development.
• Practical knowledge of Verilog/SystemVerilog.
• Practical understanding of the ASIC design flow.
• Strong background in synthesis, front-end implementation, and design-for-closure methodology.
• Practical understanding of STA, timing constraints, and timing arcs.
• Experience with CDC/RDC/Lint concepts and signoff-ready design practices.
• Ability to collaborate effectively with verification, implementation, and validation teams.
• Scripting experience in Python, Tcl, Perl, or Shell.
• Strong communication and cross-team collaboration skills.
  
  

Nice to Have

• Experience with PCIe, USB, or UCIe-based designs.
• Experience with Verdi or other waveform/debug tools.
• Exposure to UVM or formal verification concepts.
• Experience with interface IP or protocol bring-up.
• Prior experience in a global product engineering environment.
  
  

Who You Are

• You can sit in a design review, absorb feedback from three different teams, and walk out with a clear plan
• You do not wait for perfect specs, you work with what you have and ask the right questions
• You can explain a timing closure issue to an implementation engineer and a CDC violation to a verification engineer in the same afternoon
• You are comfortable debugging a waveform in Verdi to find the one-cycle glitch that breaks the protocol handshake
• You write scripts because running the same check manually 47 times is not how you want to spend your week
  
  

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards And Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.