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Lattice

Lattice

Empowering the edge with low-power FPGAs and programmable solutions.

๐Ÿ“ San Francisco, California

34 Open Positions
5 Active Locations
Posted
Top Employer

About Lattice

Lattice designs low-power FPGAs and programmable logic devices, serving markets such as communications, automotive, and industrial automation from its headquarters in Hillsboro, Oregon. The Lattice Nexus and MachXO families are key products that enable efficient processing and connectivity in edge applications. Engineering disciplines include digital design, analog design, and verification, focusing on optimizing power consumption and performance in embedded systems. With a commitment to innovation, Lattice employs a diverse team of engineers who tackle challenges in SoC design and integration, ensuring robust solutions for a wide range of applications.

Current Job Openings

34 jobs

All Lattice Job Openings

  • Lattice logo

    SW QA Engineer

    @ Lattice

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog VHDL
    View SW QA Engineer
  • Lattice logo

    SOC RTL Design Engineer

    @ Lattice

    ๐Ÿ“Maharashtra, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA Verilog
    View SOC RTL Design Engineer
  • Lattice logo

    SOC RTL Design Engineer

    @ Lattice

    ๐Ÿ“pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View SOC RTL Design Engineer
  • Lattice logo

    AI Architect โ€“ EDA & FPGA Software Development hot job

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    AI FPGA EDA
    View AI Architect โ€“ EDA & FPGA Software Development
  • Lattice logo

    Silicon Validation Tech Lead โ€“ Next-Gen FPGA hot job

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA DDR PCIe
    View Silicon Validation Tech Lead โ€“ Next-Gen FPGA
  • Lattice logo

    Embedded SW Dev Engineer

    @ Lattice

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C++ Python Verilog
    View Embedded SW Dev Engineer
  • Lattice logo

    Embedded SW Dev Engineer

    @ Lattice

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    C/C++ Python Verilog
    View Embedded SW Dev Engineer
  • Lattice logo

    SOC Design Engineer

    @ Lattice

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC Verilog FPGA
    View SOC Design Engineer
  • Lattice logo

    SOC Design Engineer

    @ Lattice

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SoC Verilog FPGA
    View SOC Design Engineer
  • Lattice logo

    SOC Design Engineer

    @ Lattice

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    verilog SystemVerilog FPGA
    View SOC Design Engineer
  • Lattice logo

    Staff SoC RTL Designer

    @ Lattice

    ๐Ÿ“Maharashtra, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA CPLD
    View Staff SoC RTL Designer
  • Lattice logo

    Staff SW Dev Eng hot job

    @ Lattice

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA C++ Python
    View Staff SW Dev Eng
  • Lattice logo

    Staff EDA Engineer โ€“ RTL Front End Tools & Methodologies

    @ Lattice

    ๐Ÿ“pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    EDA RTL FPGA
    View Staff EDA Engineer โ€“ RTL Front End Tools & Methodologies
  • Lattice logo

    SW QA Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog SystemVerilog VHDL
    View SW QA Engineer
  • Lattice logo

    Staff SW Dev Eng

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA C++ Python
    View Staff SW Dev Eng
  • Lattice logo

    Senior Director Analog IC Design hot job

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal PLLs
    View Senior Director Analog IC Design
  • Lattice logo

    Sr. Staff RTL Eng

    @ Lattice

    ๐Ÿ“pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA CPLD
    View Sr. Staff RTL Eng
  • Lattice logo

    Senior Analog IC Design Engineer

    @ Lattice

    ๐Ÿ“Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal SerDes
    View Senior Analog IC Design Engineer
  • Lattice logo

    Analog Design Engineer 4

    @ Lattice

    ๐Ÿ“Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal PLLs
    View Analog Design Engineer 4
  • Lattice logo

    Sr. Embedded Software Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA CPLD programmable
    View Sr. Embedded Software Engineer
  • Lattice logo

    Staff SoC RTL Designer

    @ Lattice

    ๐Ÿ“pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SoC RTL FPGA
    View Staff SoC RTL Designer
  • Lattice logo

    HDL Design/Verification Engineer hot job

    @ Lattice

    ๐Ÿ“Malaysia, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    HDL Verilog VHDL
    View HDL Design/Verification Engineer
  • Lattice logo

    Staff EDA Engineer โ€“ RTL Front End Tools & Methodologies

    @ Lattice

    ๐Ÿ“Maharashtra, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA EDA
    View Staff EDA Engineer โ€“ RTL Front End Tools & Methodologies
  • Lattice logo

    Senior Staff SW Dev Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA C++ Python
    View Senior Staff SW Dev Engineer
  • Lattice logo

    Senior Applications Engineer โ€“ FPGA Tools

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA VHDL Verilog
    View Senior Applications Engineer โ€“ FPGA Tools
  • Lattice logo

    Senior Director Analog IC Design hot job

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal Cadence
    View Senior Director Analog IC Design
  • Lattice logo

    Sr. Staff RTL Eng

    @ Lattice

    ๐Ÿ“Maharashtra, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA CPLD
    View Sr. Staff RTL Eng
  • Lattice logo

    Senior Embedded Software Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ Linux Bootloader
    View Senior Embedded Software Engineer
  • Lattice logo

    Sr. Embedded Software Engineer

    @ Lattice

    ๐Ÿ“Taman Pulau Pinang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA CPLD programmable
    View Sr. Embedded Software Engineer
  • Lattice logo

    Senior Analog IC Design Engineer

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog mixed-signal SerDes
    View Senior Analog IC Design Engineer
  • Lattice logo

    Analog Design Engineer 4

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SerDes PLLs ADC
    View Analog Design Engineer 4
  • Lattice logo

    Sr Staff / Principal Engineer โ€“ FPGA Circuit & Behavioral Modeling

    @ Lattice

    ๐Ÿ“Pune District, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog VHDL
    View Sr Staff / Principal Engineer โ€“ FPGA Circuit & Behavioral Modeling
  • Lattice logo

    Sr / Staff Custom Memory Design Engineer โ€“ SRAM & FPGA CRAM

    @ Lattice

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SRAM FPGA CMOS
    View Sr / Staff Custom Memory Design Engineer โ€“ SRAM & FPGA CRAM
  • Lattice logo

    Silicon Bring-Up & Validation Engineer โ€“ Next-Gen FPGA

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog D-PHY
    View Silicon Bring-Up & Validation Engineer โ€“ Next-Gen FPGA
  • Previously posted positions that may provide insight into Lattice's hiring patterns

  • Expired
    Lattice logo

    Analog Design Engineer 4

    @ Lattice

    ๐Ÿ“Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal PLLs
    View details
    View Analog Design Engineer 4
  • Expired
    Lattice logo

    Senior Analog IC Design Engineer

    @ Lattice

    ๐Ÿ“Taiwan, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal FinFET
    View details
    View Senior Analog IC Design Engineer
  • Expired
    Lattice logo

    HDL Design/Verification Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    HDL Verilog VHDL
    View details
    View HDL Design/Verification Engineer
  • Expired
    Lattice logo

    Senior Analog IC Design Engineer

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal PLLs
    View details
    View Senior Analog IC Design Engineer
  • Expired
    Lattice logo

    Analog Design Engineer 4

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog mixed-signal SerDes
    View details
    View Analog Design Engineer 4
  • Expired
    Lattice logo

    Staff EDA Engineer โ€“ RTL Front End Tools & Methodologies hot job

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL EDA Python
    View details
    View Staff EDA Engineer โ€“ RTL Front End Tools & Methodologies
  • Expired
    Lattice logo

    Embedded Software Intern

    @ Lattice

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š intern
    โฑ๏ธŽ internship
    C C++ MCU
    View details
    View Embedded Software Intern
  • Expired
    Lattice logo

    Embedded Software Intern

    @ Lattice

    ๐Ÿ“Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    C C++ MCU
    View details
    View Embedded Software Intern
  • Expired
    Lattice logo

    Senior Director Analog IC Design hot job

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal PLL
    View details
    View Senior Director Analog IC Design
  • Expired
    Lattice logo

    Sr. Staff RTL Eng

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog FPGA
    View details
    View Sr. Staff RTL Eng
  • Expired
    Lattice logo

    Principal Engineer โ€“ UI Architect hot job

    @ Lattice

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    Java Swing EDA
    View details
    View Principal Engineer โ€“ UI Architect
  • Expired
    Lattice logo

    Principal RTL Engineer โ€“ FPGA Debug & EDA Architecture

    @ Lattice

    ๐Ÿ“Hyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    RTL FPGA SystemVerilog
    View details
    View Principal RTL Engineer โ€“ FPGA Debug & EDA Architecture
  • Expired
    Lattice logo

    Senior Director โ€“ IC Design

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal silicon
    View details
    View Senior Director โ€“ IC Design
  • Expired
    Lattice logo

    Sr.Staff RTL Eng

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog FPGA
    View details
    View Sr.Staff RTL Eng
  • Expired
    Lattice logo

    Staff / Lead Engineer - FPGA Systems Applications Engineering

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA RTL UVM
    View details
    View Staff / Lead Engineer - FPGA Systems Applications Engineering
  • Expired
    Lattice logo

    FPGA SW Tool Intern

    @ Lattice

    ๐Ÿ“George Town, Cayman Islands
    ๐Ÿ“Š internship
    โฑ๏ธŽ internship
    FPGA C++ Python
    View details
    View FPGA SW Tool Intern
  • Expired
    Lattice logo

    Rtl / Digital Design Engineer

    @ Lattice

    ๐Ÿ“India, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog FPGA
    View details
    View Rtl / Digital Design Engineer
  • Expired
    Lattice logo

    Robotics and Humanoid Business Development

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    AI sensor robotics
    View details
    View Robotics and Humanoid Business Development
  • Expired
    Lattice logo

    Applications Engineer โ€“ FPGA Tools

    @ Lattice

    ๐Ÿ“San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA Verilog VHDL
    View details
    View Applications Engineer โ€“ FPGA Tools
  • Expired
    Lattice logo

    Senior Embedded Software Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C/C++ Linux RTOS
    View details
    View Senior Embedded Software Engineer
  • Expired
    Lattice logo

    Sr. Embedded Software Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    C++ device Linux
    View details
    View Sr. Embedded Software Engineer
  • Expired
    Lattice logo

    SW Development Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA C++ Python
    View details
    View SW Development Engineer
  • Expired
    Lattice logo

    Senior QA Engineer โ€“ FPGA Place & Route Validation

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA P&R Tcl
    View details
    View Senior QA Engineer โ€“ FPGA Place & Route Validation
  • Expired
    Lattice logo

    Staff SoC RTL Designer

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA SoC
    View details
    View Staff SoC RTL Designer
  • Expired
    Lattice logo

    Analog Design Engineer 4

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog mixed-signal IC
    View details
    View Analog Design Engineer 4
  • Expired
    Lattice logo

    Senior Analog IC Design Engineer

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog mixed-signal PLLs
    View details
    View Senior Analog IC Design Engineer
  • Expired
    Lattice logo

    Embedded Firmware Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    SystemC C++ TLM
    View details
    View Embedded Firmware Engineer
  • Expired
    Lattice logo

    SW Development Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA C++ Python
    View details
    View SW Development Engineer
  • Expired
    Lattice logo

    Design Verification Engineer

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA SystemVerilog UVM
    View details
    View Design Verification Engineer
  • Expired
    Lattice logo

    Sr Design Verification Engineer

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA UVM SystemVerilog
    View details
    View Sr Design Verification Engineer
  • Expired
    Lattice logo

    Analog Design Engineer

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog mixed-signal SerDes
    View details
    View Analog Design Engineer
  • Expired
    Lattice logo

    SW QA Engineer โ€“ FPGA Timing & Hardware Testing

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA Python Tcl
    View details
    View SW QA Engineer โ€“ FPGA Timing & Hardware Testing
  • Expired
    Lattice logo

    HDL Design/Verification Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Verilog VHDL SystemVerilog
    View details
    View HDL Design/Verification Engineer
  • Expired
    Lattice logo

    Senior Design Verification Engineer

    @ Lattice

    ๐Ÿ“Muntinlupa City, Philippines ๐Ÿ‡ต๐Ÿ‡ญ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    verification SystemVerilog UVM
    View details
    View Senior Design Verification Engineer
  • Expired
    Lattice logo

    SoC RTL Designer

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View SoC RTL Designer
  • Expired
    Lattice logo

    Staff SoC RTL Designer

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA Verilog
    View details
    View Staff SoC RTL Designer
  • Expired
    Lattice logo

    Staff Design Verification Engineer

    @ Lattice

    ๐Ÿ“Muntinlupa City, Philippines ๐Ÿ‡ต๐Ÿ‡ญ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    UVM SystemVerilog ASIC
    View details
    View Staff Design Verification Engineer
  • Expired
    Lattice logo

    Principle RTL Engineer hot job

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š principal
    โฑ๏ธŽ full-time
    RTL FPGA Verilog
    View details
    View Principle RTL Engineer
  • Expired
    Lattice logo

    Sr Engineer - RTL Design

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View Sr Engineer - RTL Design
  • Expired
    Lattice logo

    Embedded Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    RTL VHDL Verilog
    View details
    View Embedded Engineer
  • Expired
    Lattice logo

    Engineer - RTL Design

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA Verilog SystemVerilog
    View details
    View Engineer - RTL Design
  • Expired
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    Engineer - Firmware Design

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA C++ Python
    View details
    View Engineer - Firmware Design
  • Expired
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    Soft SOC Design and Integration Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    SOC FPGA Integration
    View details
    View Soft SOC Design and Integration Engineer
  • Expired
    Lattice logo

    Senior Staff RTL/Integration Design Engineer hot job

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL Verilog SystemVerilog
    View details
    View Senior Staff RTL/Integration Design Engineer
  • Expired
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    Senior Staff Analog Design Engineer

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Analog mixed-signal SerDes
    View details
    View Senior Staff Analog Design Engineer
  • Expired
    Lattice logo

    Senior Staff Analog Design Engineer

    @ Lattice

    ๐Ÿ“Taipei, Taiwan ๐Ÿ‡น๐Ÿ‡ผ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    analog mixed-signal SerDes
    View details
    View Senior Staff Analog Design Engineer
  • Expired
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    SoC RTL Designer

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    RTL FPGA Verilog
    View details
    View SoC RTL Designer
  • Expired
    Lattice logo

    Soft SOC Design and Integration Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    FPGA Verilog AXI
    View details
    View Soft SOC Design and Integration Engineer
  • Expired
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    Staff Design Verification Engineer

    @ Lattice

    ๐Ÿ“Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ
    ๐Ÿ“Š senior
    โฑ๏ธŽ full-time
    Python HDL FPGA
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    View Staff Design Verification Engineer
  • Expired
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    Design Verification Engineer

    @ Lattice

    ๐Ÿ“Pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ
    ๐Ÿ“Š mid-level
    โฑ๏ธŽ full-time
    FPGA SystemVerilog UVM
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    View Design Verification Engineer
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Company Info
Employees 501-1000
Founded 2015
Type Public
Stock LSCC
Glassdoor 4.2
Connect
Active Hiring Locations
๐Ÿ“ San Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ 6
๐Ÿ“ Shanghai, China ๐Ÿ‡จ๐Ÿ‡ณ 5
๐Ÿ“ Penang, Malaysia ๐Ÿ‡ฒ๐Ÿ‡พ 5
๐Ÿ“ Maharashtra, India ๐Ÿ‡ฎ๐Ÿ‡ณ 4
๐Ÿ“ pune, India ๐Ÿ‡ฎ๐Ÿ‡ณ 4
Top Roles
Embedded Software Engineer (7) SoC Design Engineer (7) Embedded Systems Engineer (7) Analog Design Engineer (6) FPGA Engineer (3)
Key Skills
FPGA Verilog RTL SystemVerilog EDA Python mixed-signal C++
Seniority Levels
senior (29) mid-level (5)
Work Arrangement
On-site (34)

About Lattice

Lattice designs low-power FPGAs and programmable logic devices, serving markets such as communications, automotive, and industrial automation from its headquarters in Hillsboro, Oregon. The Lattice Nexus and MachXO families are key products that enable efficient processing and connectivity in edge applications. Engineering disciplines include digital design, analog design, and verification, focusing on optimizing power consumption and performance in embedded systems. With a commitment to innovation, Lattice employs a diverse team of engineers who tackle challenges in SoC design and integration, ensuring robust solutions for a wide range of applications.

Lattice Career Opportunities

Lattice currently has 34 active embedded systems positions spanning 5 countries. All positions are on-site, typical for hardware-focused roles requiring lab access and equipment. Recognized as a top-tier employer (85.0/100), Lattice offers competitive compensation and strong career development paths in embedded engineering.

Lattice Hiring Trends

* Data represents job posting activity over the past 6 months: Feb 2026 through Jul 2026

Lattice's hiring pace has moderated recently (7 openings this month vs 32 last month), which is common after major hiring pushes or as projects move from development to deployment phases.

Over the past 6 months, Lattice averaged 10.0 job postings per month, with peak hiring in Jun 2026 (32 openings). For embedded systems roles, hiring activity typically correlates with product development cycles, especially for firmware teams during pre-production phases and hardware engineers during prototyping.

Current Month
7 jobs

๐Ÿ“‰ -78% change

6-Month Average
10.0 jobs/month

Consistent hiring velocity

Peak Activity
32 jobs

Jun 2026

Required Skills at Lattice

FPGA is the most in-demand skill at Lattice, appearing in 67% of all job listings (past and present). This skill is important but not universal, indicating diverse technical needs across different product lines or teams.

Lattice's technology stack spans 99 distinct skills and tools, reflecting the multifaceted nature of embedded systems development. The broad technical diversity (99 technologies) suggests work on complex, multi-domain projects requiring both hardware and software expertise.

FPGA
67% of roles
67%
Verilog
36% of roles
36%
RTL
27% of roles
27%
SystemVerilog
24% of roles
24%
EDA
19% of roles
19%
Python
19% of roles
19%
mixed-signal
19% of roles
19%
C++
14% of roles
14%
PLLs
14% of roles
14%
Cadence
14% of roles
14%
VHDL
13% of roles
13%
analog
12% of roles
12%

Engineers joining Lattice should combine depth in key areas with adaptability. The mix of hardware skills (PCB design, schematics) and firmware expertise (RTOS, embedded C) indicates full-stack embedded development where engineers work across the hardware-software boundary. Candidates with adjacent skills (version control, testing frameworks, communication protocols) typically advance faster by contributing across the development lifecycle.

Engineering Roles at Lattice

Lattice's primary hiring focus is Embedded Software Engineer with 7 open positions. High-volume recruitment for a single role type typically indicates either a growing team building similar capabilities or a newly formed department scaling rapidly.

Multiple openings in the same discipline create advantages for new hires: stronger peer support networks, established onboarding processes, and clearer career progression paths as the team matures. Engineers often find collaborative environments more conducive to professional growth.

Embedded Software Engineer
7 positions (21%)
7
SoC Design Engineer
7 positions (21%)
7
Embedded Systems Engineer
7 positions (21%)
7
Analog Design Engineer
6 positions (18%)
6
FPGA Engineer
3 positions (9%)
3
Hardware Engineer
2 positions (6%)
2
RTL Design Engineer
1 position (3%)
1
Electrical Engineer
1 position (3%)
1

Experience level distribution: 85% of openings target senior-level engineers.

Where Lattice is Hiring

Lattice operates across 7 countries with 15 total hiring locations. Multi-geography recruitment typically indicates either distributed engineering teams, expansion into new markets, or proximity to manufacturing and customer operations.

Penang, Malaysia serves as a primary hiring hub with 21% of all roles (18 positions). Engineering capabilities are distributed relatively evenly across locations, suggesting a genuinely multi-site development model rather than a single headquarters-centric approach.

๐Ÿ‡บ๐Ÿ‡ธ
San Jose, United States
6 active jobs
6
๐Ÿ‡จ๐Ÿ‡ณ
Shanghai, China
5 active jobs
5
๐Ÿ‡ฒ๐Ÿ‡พ
Penang, Malaysia
5 active jobs
5
๐Ÿ‡ฎ๐Ÿ‡ณ
Maharashtra, India
4 active jobs
4
๐Ÿ‡ฎ๐Ÿ‡ณ
pune, India
4 active jobs
4
๐Ÿ‡ฒ๐Ÿ‡พ
Taman Pulau Pinang, Malaysia
3 active jobs
3
๐Ÿ‡น๐Ÿ‡ผ
Taiwan, Taiwan
2 active jobs
2
๐Ÿ‡น๐Ÿ‡ผ
Taipei, Taiwan
2 active jobs
2
๐Ÿ‡ฒ๐Ÿ‡พ
Malaysia, Malaysia
1 active job
1
๐Ÿ‡ฎ๐Ÿ‡ณ
Pune District, India
1 active job
1
๐Ÿ‡ฎ๐Ÿ‡ณ
Hyderabad, India
1 active job
1
๐Ÿ‡ฎ๐Ÿ‡ณ
Pune, India
16 previous jobs

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