SW QA Engineer – FPGA Timing & Hardware Testing

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Key Responsibilities

Responsibilities & Skills

• Develop and execute detailed test plans for timing analysis and hardware programming workflows, including advanced debug features (e.g., Reveal).
• Validate timing analysis accuracy and consistency across multiple FPGA device families and design constraints.
• Perform hardware board-level testing for FPGA programming, configuration, and debug tools.
• Automate test cases using scripting languages (Python, Tcl, Shell) for efficiency and repeatability.
• Simulate customer workflows: synthesis, place-and-route, timing closure, and hardware bring-up.
• Debug complex timing and hardware issues by analyzing logs, waveforms, and design reports.
• Collaborate with development teams to reproduce issues, triage defects, and verify fixes.
• Maintain regression suites and dashboards to monitor timing performance and hardware reliability.
• Provide clear, data-driven reports on validation outcomes and defect analysis.