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Synopsys Inc

ASIC Digital Design, Staff Engineer

๐Ÿ“ŒHyderabad, India ๐Ÿ‡ฎ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

At Synopsys, weโ€™re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And weโ€™re powering it all with the worldโ€™s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chipsโ€”faster. Weโ€™re the worldโ€™s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performanceโ€”eliminating months off their project schedules.

ASIC Digital Design, Staff Engineer

The ASIC Digital Design Staff Engineer will be a key member of the Synopsys Designware ARC Processor development team.

Individual contributor will be responsible for architectural and RTL design of microprocessor IP, Optimize design for performance, speed, area and power. Work with multi-site core teams. Review and improve verification test suites.

At minimum, a Bachelorโ€™s degree in engineering is required with 7+ years of digital design experience using Verilog. Strong background in RISC architectures is required. Working experience in RISC microprocessor IP design, programming at assembly and C/C++ level, DSP skills, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful

The successful candidate is expected to:

  • Design embedded RISC microprocessor IP at architectural and RTL level
  • Optimize design for performance, speed, area and power, Generate hardware benchmarks and analyse results
  • Develop standalone Verilog testbenches to verify their module
  • Debug design issues / bugs working closely with verification team
  • Maintain our current processor product line and their derivative products
  • Develop and maintain project plans. Work closely with program managers
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