Bootstrap

Synopsys Inc

ASIC Digital Design, Sr Engineer

๐Ÿ“ŒWuhan, China ๐Ÿ‡จ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

Synopsys technology is at the heart of innovations that are changing the way we live and work. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the worldโ€™s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.

Synopsys is committed to fostering an environment that treats people with respect, honesty and professionalism. Weโ€™re also committed to partnering with the communities in which we work. Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities.

Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs. Join US!

Senior ASIC Design Engineer

You would be working as part of a highly experienced mixed-signal design team, targeting the next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer and data recovery circuits is an asset. The position offers an excellent opportunity to work with an experienced team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips.

Qualifications

Must have hands-on experience in RTL design(Verilog or System Verilog)

Must have hands-on experience with multiple clock domain design

Have experience with CDC/RDC/LINT tools

Have experience in defining synthesis constraints and STA

Good understanding of digital signal processing

Good organization and communication skills for interacting between different design groups and customer support teams

Knowledge of the following will be considered as an important asset:

High-speed digital & mixed-signal design

Experience in analog design

DFT design methodologies
Other similar jobs

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

CPU Physical Design Principal Engineer

@ Qualcomm, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Analog Design Engineer - REF79515L

@ Continental, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

Staff Engineer, Digital IC Design

@ Marvell Technology, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Physical Design Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

  • Skills
  • Industry
  • Find similar jobs

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    CPU Physical Design Principal Engineer

    @ Qualcomm, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Analog Design Engineer - REF79515L

    @ Continental, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    Staff Engineer, Digital IC Design

    @ Marvell Technology, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Physical Design Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

Remote Work
Post time
Level
Employment
Industry
Apply Now โ†—