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Synopsys Inc

ASIC Digital Design, Staff Engineer

๐Ÿ“ŒYerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

At Synopsys, weโ€™re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, The cloud, 5G, The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And weโ€™re powering it all with the worldโ€™s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. The candidate will be a part of the R&D in Synopsys Die-to-Die IP Design Group at Yerevan, Armenia. This is an Individual Contributor role and offers challenges to work in a multi-site environment.

Main Responsibilities:

  • To work on the Die-to-Die protocols for commercial, Enterprise and Automotive applications.
  • Knowledge of Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality.
  • Perform Design Tasks โ€“ RTL coding, synthesis, CDC/ RDC, debug, verification etc.
  • Possible interaction with customers to discuss customersโ€™ needs and specification requirements.
  • The candidate will work in a project and team-oriented environment with teams spread across the sites, worldwide.

Key Requirements:

  • Must have BSEE in EE with 5+ years of relevant experience or MSEE with 3+ years of relevant experience.
  • Knowledge of one or more of AMBA protocols. PCIe/CXL or Die-to-Die protocols knowledge is a plus.
  • Hands on experience with architecting/ micro-architecture/ detailed design from Functional Specifications. Must have worked on control path-oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
  • Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Verification tools.
  • Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc. is a must for candidates with design background.
  • Experience with Perforce or similar revision control environment.
  • Knowledge of Perl/Shell scripts.
  • Exposure to quality processes in the context of IP design and verification is an added advantage.
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