ASIC Verification Engineer, Sr Staff

You Are:

You are a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification. You thrive in a collaborative environment and have a keen eye for detail. Your technical expertise is complemented by your ability to communicate effectively and work well within a team. You are self-motivated and enthusiastic about technology and problem-solving. With a minimum of 5 years of experience in design verification, you have honed your skills in using simulation tools, scripting languages, and advanced verification techniques. You have a solid understanding of digital and mixed-signal designs and are eager to contribute to cutting-edge technologies that enable Data Center, AI/ML, and 5G applications.

What You’ll Be Doing:

• Working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP.
• Planning tests, checklists, coverage, and assertion planning.
• Creating detailed verification environments from functional specifications.
• Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
• Writing test cases, checkers, and coverage that implement the verification test plan.
• Debugging simulations, including those of real signals modeled using SystemVerilog for analog.
• Performing RTL, GLS, and co-simulations and ensuring coverage closure.
• Participating in technical reviews and contributing actively.
• Providing customer support with the bring-up of IP in customer simulation environments.
• Following and improving development processes to ensure high-quality output.
  
  

What You’ll Need:

• BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
• 7+ years of experience in design verification.
• Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).
• Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.
• Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
  
  

Who You Are:

• Highly responsible and result-oriented.
• Excellent English communication skills, both verbal and written.
• A great team player, willing to support others.
• Self-motivated and highly enthusiastic about technology and solving problems