You will be part of the R&D in IP Group at our Tokyo IP R&D center, Japan. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers opportunities to work in a multi-site environment on Design and Verification of VLSI IP cores/ASIC/Subsystems.
Academic Qualification requirements
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Must be in the final year towards acquiring a formal Bachelor's in Engineering degree (BTech/BE) in EE/EC or similar; or
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Must be in the final year towards acquiring a formal Master's in Engineering postgraduate degree (MTech/ME) in VLSI/Micro Electronics /Computer Engineering or similar.
Job Responsibilities:
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Front end VLSI development from specification to implementation
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The candidate will get to work on one or more aspects of IP development including Specification, Architecting, Design, Verification across domains.
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Design Tasks - RTL coding of design, synthesis, CDC analysis, debug, Test development etc.
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Verification Tasks - System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the lasted methodologies such as UVM, Formal verification etc.
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State Of the art tools and methodologies for IP design including FPGA prototyping
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Latest Protocol standards including AMBA, DDR, PCIe, CXL, CCIX
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Application space across high performance mobile computing and communication devices, Servers etc.
Knowledge Skills
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Excellent fundamentals in Digital electronics
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Proficiency in structured programming languages such as C, C++, Python
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Preferred Exposure to Verilog, VHDL, System Verilog and VLSI Design/verification methodologies and tools
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Good problem-solving skills and analytical abilities.
Soft Skills
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Good team player, social skills and communication skills.
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High levels of motivation and self-propulsion
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Aptitude to pursue a career in VLSI field.