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Synopsys Inc

ASIC Digital Design, Engineer

📌Tokyo, Japan 🇯🇵

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⏱︎ full-time

🧙‍♂️ entry-level

You will be part of the R&D in IP Group at our Tokyo IP R&D center, Japan. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers opportunities to work in a multi-site environment on Design and Verification of VLSI IP cores/ASIC/Subsystems.

Academic Qualification requirements

  • Must be in the final year towards acquiring a formal Bachelor's in Engineering degree (BTech/BE) in EE/EC or similar; or
  • Must be in the final year towards acquiring a formal Master's in Engineering postgraduate degree (MTech/ME) in VLSI/Micro Electronics /Computer Engineering or similar.

Job Responsibilities:

  • Front end VLSI development from specification to implementation
  • The candidate will get to work on one or more aspects of IP development including Specification, Architecting, Design, Verification across domains.
  • Design Tasks - RTL coding of design, synthesis, CDC analysis, debug, Test development etc.
  • Verification Tasks - System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the lasted methodologies such as UVM, Formal verification etc.
  • State Of the art tools and methodologies for IP design including FPGA prototyping
  • Latest Protocol standards including AMBA, DDR, PCIe, CXL, CCIX
  • Application space across high performance mobile computing and communication devices, Servers etc.

Knowledge Skills

  • Excellent fundamentals in Digital electronics
  • Proficiency in structured programming languages such as C, C++, Python
  • Preferred Exposure to Verilog, VHDL, System Verilog and VLSI Design/verification methodologies and tools
  • Good problem-solving skills and analytical abilities.

Soft Skills

  • Good team player, social skills and communication skills.
  • High levels of motivation and self-propulsion
  • Aptitude to pursue a career in VLSI field.
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