altera
altera
Shaping the Future with Tech
📍 San Jose, CA, USA
About altera
Altera designs and manufactures FPGAs, CPLDs, and SoCs, primarily serving the telecommunications, automotive, and industrial markets. Headquartered in San Jose, California, Altera's products enable high-performance computing and signal processing applications. The engineering team focuses on digital design, hardware verification, and embedded systems development. Engineers work on optimizing FPGA architectures and developing software tools for design automation. Altera's significant presence in the FPGA market is marked by its innovative product lines and extensive customer base.
Current Job Openings
19 jobsAll altera Job Openings
-
FPGA Compiler Engineer
@ altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA EDA ASICView FPGA Compiler Engineer -
FPGA Configuration Architect
@ altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA JTAG SPIView FPGA Configuration Architect -
FPGA Development Tools Engineer
@ altera
📍Marlow, United Kingdom 🇬🇧📊 mid-level⏱︎ full-timeFPGA C/C++ VerilogView FPGA Development Tools Engineer -
FPGA Silicon Validation Engineer
@ altera
📍San Jose, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA silicon validationView FPGA Silicon Validation Engineer -
Senior FPGA Security Architect– Aerospace, Defense & Government
@ altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA security encryptionView Senior FPGA Security Architect– Aerospace, Defense & Government -
Digital Design / FPGA Engineering - Intern
@ altera
📍San Jose, United States 🇺🇸📊 intern⏱︎ internshipRTL SystemVerilog FPGAView Digital Design / FPGA Engineering - Intern -
FPGA SW Validation Engineer
@ altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA SW Validation Engineer -
FPGA Development Tools Engineer – Synthesis
@ altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA Verilog VHDLView FPGA Development Tools Engineer – Synthesis -
Senior FPGA Compiler Engineer
@ altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA EDA routingView Senior FPGA Compiler Engineer -
FPGA Development Tools Engineer – Synthesis
@ altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA Verilog VHDLView FPGA Development Tools Engineer – Synthesis -
Senior FPGA Compiler Engineer
@ altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA EDA C/C++View Senior FPGA Compiler Engineer -
FPGA Digital Design & Verification - Intern
@ altera
📍San Jose, United States 🇺🇸📊 entry-level⏱︎ internshipSystemVerilog UVM ModelSimView FPGA Digital Design & Verification - Intern -
Manager, FPGA Synthesis
@ altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA RTL synthesisView Manager, FPGA Synthesis -
FPGA Post Silicon Validation Engineer - Configuration, Security and HPS
@ altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA SoC securityView FPGA Post Silicon Validation Engineer - Configuration, Security and HPS -
High Level Synthesis Compiler Engineer
@ altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeC++ LLVM MLIRView High Level Synthesis Compiler Engineer -
FPGA Development Tools Engineer - Graduate Intern
@ altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ internshipFPGA Quartus timingView FPGA Development Tools Engineer - Graduate Intern -
FPGA Machine Learning Engineering - Graduate Intern
@ altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ internshipFPGA Verilog VHDLView FPGA Machine Learning Engineering - Graduate Intern -
FPGA Post Silicon Validation Engineer
@ altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA SoC validationView FPGA Post Silicon Validation Engineer -
FPGA Post Silicon Validation Intern
@ altera
📍Penang, Malaysia 🇲🇾📊 intern⏱︎ internshipFPGA PCB measurementView FPGA Post Silicon Validation Intern -
Expired
FPGA Configuration and Security UX Validation Engineer
@ altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA firmware validationView FPGA Configuration and Security UX Validation EngineerView details -
Expired
Senior SoC Design Verification Engineer
@ altera
📍Madhapur, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM VerilogView Senior SoC Design Verification EngineerView details -
Expired
FPGA Post Silicon Validation Engineer - Configuration, Security and HPS
@ altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA SoC securityView FPGA Post Silicon Validation Engineer - Configuration, Security and HPSView details -
Expired
FPGA Silicon Design Verification Engineer
@ altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSystemVerilog UVM PerlView FPGA Silicon Design Verification EngineerView details -
Expired
FPGA Circuit Design Engineer
@ altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA SoC RTLView FPGA Circuit Design EngineerView details -
Expired
FPGA Architect Undergrad Intern
@ altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ internshipFPGA AWS PythonView FPGA Architect Undergrad InternView details -
Expired
FPGA Development Tools Engineer — College Graduate
@ altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeFPGA EDA C++View FPGA Development Tools Engineer — College GraduateView details -
Expired
FPGA Development Tools Engineer
@ altera
📍San Jose, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA C/C++ PythonView FPGA Development Tools EngineerView details -
Expired
FPGA Development Tools Engineer - College Graduate
@ altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeFPGA EDA TclView FPGA Development Tools Engineer - College GraduateView details -
Expired
FPGA Development Tools Engineer
@ altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ full-timeC/C++ Python PerlView FPGA Development Tools EngineerView details -
Expired
FPGA Development Tools Manager
@ altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA synthesis debugView FPGA Development Tools ManagerView details -
Expired
FPGA Development Tools Engineer
@ altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA SystemVerilog VHDLView FPGA Development Tools EngineerView details -
Expired
FPGA Development Tools Engineer - Intern
@ altera
📍San Jose, United States 🇺🇸📊 entry-level⏱︎ internshipFPGA Quartus HDLView FPGA Development Tools Engineer - InternView details -
Expired
FPGA Compiler Software Engineer
@ altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA C++ EDAView FPGA Compiler Software EngineerView details -
Expired
FPGA Silicon Validation Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeTransceiver validation PCIeView FPGA Silicon Validation EngineerView details -
Expired
Robotics Solutions Architect - Intern
@ Altera
📍San Jose, United States 🇺🇸📊 intern⏱︎ internshipFPGA Robotics C/C++View Robotics Solutions Architect - InternView details -
Expired
FPGA Silicon Design Engineer
@ Altera
📍San Jose, United States of America 🇺🇸📊 senior⏱︎ full-timeRTL SystemVerilog VerilogView FPGA Silicon Design EngineerView details -
Expired
FPGA Hardware Board Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA PCB EDAView FPGA Hardware Board Design EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA C++ PythonView FPGA Development Tools EngineerView details -
Expired
Firmware Developer
@ Altera
📍San Jose, United States of America 🇺🇸📊 senior⏱︎ full-timeC++ assembly RTOSView Firmware DeveloperView details -
Expired
FPGA Design & DV Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 entry-level⏱︎ contractVHDL Verilog SystemVerilogView FPGA Design & DV EngineerView details -
Expired
FPGA Firmware User Experience Validation Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA Python JenkinsView FPGA Firmware User Experience Validation EngineerView details -
Expired
FPGA IP Design and Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 entry-level⏱︎ internshipFPGA Verilog VHDLView FPGA IP Design and Verification EngineerView details -
Expired
Senior Principal Engineer, Design Verification
@ Altera
📍San Jose, United States 🇺🇸📊 principal⏱︎ full-timePCIe SystemVerilog UVMView Senior Principal Engineer, Design VerificationView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timelayout verification powerView Analog Layout Design EngineerView details -
Expired
SOC Timing Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timetiming FPGA EDAView SOC Timing EngineerView details -
Expired
FPGA Silicon Validation Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA PHY MIPIView FPGA Silicon Validation EngineerView details -
Expired
FPGA Tools Engineer - Intern
@ Altera
📍San Jose, United States of America 🇺🇸📊 intern⏱︎ internshipAI Quartus JavaView FPGA Tools Engineer - InternView details -
Expired
Senior Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA PCIe SystemVerilogView Senior Design Verification EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeAnalog Layout SerDesView Analog Layout Design EngineerView details -
Expired
RTL Front End Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeRTL FPGA LINTView RTL Front End Design EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeUVM SystemVerilog PCIeView Design Verification EngineerView details -
Expired
FPGA SW Validation Engineer - Sr./Lead
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA SW Validation Engineer - Sr./LeadView details -
Expired
FPGA Silicon Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA RTL VLSIView FPGA Silicon Design EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeCAD EDA PLLView Analog Layout Design EngineerView details -
Expired
FPGA SW Validation Engineer - Synthesis
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA SW Validation Engineer - SynthesisView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA C++ PythonView FPGA Development Tools EngineerView details -
Expired
FPGA IP Validation engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeVLSI FPGA ValidationView FPGA IP Validation engineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeanalog mixed-signal EDAView Analog Layout Design EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeanalog IC DRCView Analog Layout Design EngineerView details -
Expired
FPGA IP Software Design Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA SystemVerilog VerilogView FPGA IP Software Design EngineerView details -
Expired
FPGA Post Silicon Validation Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeFPGA JTAG HPSView FPGA Post Silicon Validation EngineerView details -
Expired
FPGA Silicon Validation Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA MIPI PCIeView FPGA Silicon Validation EngineerView details -
Expired
SOC Timing Engineer - College Graduate
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeSTA DFT timingView SOC Timing Engineer - College GraduateView details -
Expired
Design Verification Engineer
@ Altera
📍Hyderabad, India 🇮🇳📊 mid-level⏱︎ full-timeUVM SystemVerilog VerilogView Design Verification EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA Verilog CMOSView FPGA Circuit Design EngineerView details -
Expired
Front End ASIC RTL/Logic Senior Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeRTL HDL STAView Front End ASIC RTL/Logic Senior Design EngineerView details -
Expired
Senior SoC Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM SystemVerilogView Senior SoC Design Verification EngineerView details -
Expired
FPGA IP Software Design Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA SystemVerilog VerilogView FPGA IP Software Design EngineerView details -
Expired
Embedded Solutions-Intern
@ Altera
📍San Jose, United States 🇺🇸📊 intern⏱︎ internshipFPGA SoC C++View Embedded Solutions-InternView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA Verilog CMOSView FPGA Circuit Design EngineerView details -
Expired
FPGA Design & DV Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 entry-level⏱︎ contractVHDL Verilog SystemVerilogView FPGA Design & DV EngineerView details -
Expired
FPGA Customer Quality Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA ASIC DDRView FPGA Customer Quality EngineerView details -
Expired
FPGA Post Silicon Validation Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeFPGA JTAG SecurityView FPGA Post Silicon Validation EngineerView details -
Expired
IP Design Verification Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeRTL UVM VerilogView IP Design Verification EngineerView details -
Expired
Staff Embedded Linux Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeLinux kernel SoCView Staff Embedded Linux EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSystemVerilog UVM PythonView Design Verification EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeC++ DMA I2CView FPGA Development Tools EngineerView details -
Expired
Analog Layout Designer - Student
@ Altera
📍Haifa District, Israel 🇮🇱📊 entry-level⏱︎ internshipanalog layout DRCView Analog Layout Designer - StudentView details -
Expired
Hardware SOC Functional Safety Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeFMEA SysML FMEDAView Hardware SOC Functional Safety EngineerView details -
Expired
FPGA Silicon Validation Engineer
@ Altera
📍Austin, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA silicon validationView FPGA Silicon Validation EngineerView details -
Expired
FPGA Silicon Validation Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeFPGA SoC RTLView FPGA Silicon Validation EngineerView details -
Expired
Senior SoC Integration Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timephysical design scriptingView Senior SoC Integration EngineerView details -
Expired
Senior Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeVerilog SystemVerilog UVMView Senior Design Verification EngineerView details -
Expired
FPGA Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 entry-level⏱︎ contractFPGA VHDL VerilogView FPGA Design Verification EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA C++ PythonView FPGA Development Tools EngineerView details -
Expired
Senior SoC Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM SystemVerilogView Senior SoC Design Verification EngineerView details -
Expired
Senior SoC Design Verification Engineer
@ Altera
📍Penang, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM SystemVerilogView Senior SoC Design Verification EngineerView details -
Expired
Senior SoC Design Verification Engineer
@ Altera
📍Penang, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM SystemVerilogView Senior SoC Design Verification EngineerView details -
Expired
Sr. SoC Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM SystemVerilogView Sr. SoC Design Verification EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timelayout verification ESDView Analog Layout Design EngineerView details -
Expired
Internship – FPGA Hardware Design Engineer
@ Altera
📍Marlow, United Kingdom 🇬🇧📊 entry-level⏱︎ internshipFPGA Verilog VHDLView Internship – FPGA Hardware Design EngineerView details -
Expired
Lead Design Verification Engineer
@ Altera
📍Greater Delhi Area, India 🇮🇳📊 senior⏱︎ full-timeFPGA UVM SystemVerilogView Lead Design Verification EngineerView details -
Expired
Lead Design Verification Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA SystemVerilog verificationView Lead Design Verification EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍Shanghai, China 🇨🇳📊 mid-level⏱︎ full-timeUVM SystemVerilog TCLView Design Verification EngineerView details -
Expired
FPGA Design & DV Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 entry-level⏱︎ contractVHDL Verilog TclView FPGA Design & DV EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ contractFPGA HLS OneAPIView FPGA Development Tools EngineerView details -
Expired
FPGA SW Validation Engineer - Synthesis
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA SW Validation Engineer - SynthesisView details -
Expired
FPGA Post Silicon Validation Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timePCIe FPGA VerilogView FPGA Post Silicon Validation EngineerView details -
Expired
FPGA Board Applications Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA PCIe EthernetView FPGA Board Applications EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA VLSI RTLView FPGA Circuit Design EngineerView details -
Expired
FPGA IP Design Engineer Intern
@ Altera
📍Toronto, Canada 🇨🇦📊 internship⏱︎ internshipFPGA RTL VerilogView FPGA IP Design Engineer InternView details -
Expired
Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSystemVerilog UVM HDLView Design Verification EngineerView details -
Expired
Design Verification Engineer/Lead
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeUVM SystemVerilog EthernetView Design Verification Engineer/LeadView details -
Expired
SoC Frontend Integration Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeRTL Verilog SystemVerilogView SoC Frontend Integration EngineerView details -
Expired
Firmware Development Engineer
@ Altera
📍Jerusalem District, Israel 🇮🇱📊 mid-level⏱︎ full-timeFirmware SERDES DSPView Firmware Development EngineerView details -
Expired
Hardware SOC Functional Safety Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeFMEA SysML FMEDAView Hardware SOC Functional Safety EngineerView details -
Expired
Embedded Solutions-Intern
@ Altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ internshipFPGA C C++View Embedded Solutions-InternView details -
Expired
Firmware Functional Safety Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timefirmware safety IECView Firmware Functional Safety EngineerView details -
Expired
FPGA Board Farm Lead Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA Quartus JTAGView FPGA Board Farm Lead EngineerView details -
Expired
FPGA Silicon Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeSystemVerilog UVM PythonView FPGA Silicon Design Verification EngineerView details -
Expired
FPGA Silicon Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM SystemVerilogView FPGA Silicon Design Verification EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ contractSystemVerilog UVM FPGAView Design Verification EngineerView details -
Expired
FPGA Silicon Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA RTL AMBAView FPGA Silicon Design EngineerView details -
Expired
Lead Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA verification SystemVerilogView Lead Design Verification EngineerView details -
Expired
Sr. SoC Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSoC UVM SystemVerilogView Sr. SoC Design Verification EngineerView details -
Expired
Lead Design Verification Engineer
@ Altera
📍Penang, India 🇮🇳📊 senior⏱︎ full-timeFPGA SystemVerilog OVMView Lead Design Verification EngineerView details -
Expired
Lead Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA Verilog OVMView Lead Design Verification EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA VLSI RTLView FPGA Circuit Design EngineerView details -
Expired
DSP Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeDSP FPGA RTLView DSP Design EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Haifa District, Israel 🇮🇱📊 mid-level⏱︎ full-timeAnalog Layout CircuitView Analog Layout Design EngineerView details -
Expired
FPGA IO Front End Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA RTL STAView FPGA IO Front End Design EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Greater Delhi Area, India 🇮🇳📊 senior⏱︎ full-timeFPGA CMOS circuitView FPGA Circuit Design EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA VLSI RTLView FPGA Circuit Design EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA EDA CadenceView Analog Layout Design EngineerView details -
Expired
AI Engineer - FPGA Design Tools
@ Altera
📍San Jose, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA AI PythonView AI Engineer - FPGA Design ToolsView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA CMOS SPICEView FPGA Circuit Design EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Haifa District, Israel 🇮🇱📊 senior⏱︎ full-timeEDA DRC LVSView Analog Layout Design EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA VLSI RTLView FPGA Circuit Design EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timelayout FPGA EDAView Analog Layout Design EngineerView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeFPGA VHDL VerilogView FPGA IP Software Development EngineerView details -
Expired
FPGA Silicon Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA SoC verificationView FPGA Silicon Design Verification EngineerView details -
Expired
SoC & FPGA Performance Architect
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeC++ SystemC TLM2.0View SoC & FPGA Performance ArchitectView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA IP Software Development EngineerView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA IP Software Development EngineerView details -
Expired
Firmware Developer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeC++ FPGA RTOSView Firmware DeveloperView details -
Expired
SoC Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeSystemVerilog UVM AIView SoC Design Verification EngineerView details -
Expired
SoC Design Verification Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeSystemVerilog UVM verificationView SoC Design Verification EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeSystemVerilog UVM FPGAsView Design Verification EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA SystemVerilog UVMView Design Verification EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 mid-level⏱︎ full-timeverification SystemVerilog OVMView Design Verification EngineerView details -
Expired
FPGA IP Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA SystemVerilog UVMView FPGA IP Verification EngineerView details -
Expired
Senior Staff FPGA Compiler Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA Quartus EDAView Senior Staff FPGA Compiler Software EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeC++ FPGA DMAView FPGA Development Tools EngineerView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA C++ PythonView FPGA IP Software Development EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA VLSI RTLView FPGA Circuit Design EngineerView details -
Expired
Silicon Design Verification Engineer
@ Altera
📍Copenhagen, Denmark 🇩🇰📊 senior⏱︎ full-timeUVM SystemVerilog CView Silicon Design Verification EngineerView details -
Expired
Embedded Applications Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA FreeRTOS LinuxView Embedded Applications EngineerView details -
Expired
High Level Synthesis Compiler Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeHLS MLIR ClangView High Level Synthesis Compiler EngineerView details -
Expired
Graduate Talent - FPGA Application Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ contractFPGA Quartus TCLView Graduate Talent - FPGA Application EngineerView details -
Expired
Senior SOC Timing Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timetiming TCL PythonView Senior SOC Timing EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA EDA DRCView Analog Layout Design EngineerView details -
Expired
Senior FPGA System Level Applications Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA PCIe EthernetView Senior FPGA System Level Applications EngineerView details -
Expired
Embedded Software Engineer
@ Altera
📍Massachusetts, United States 🇺🇸📊 senior⏱︎ full-timeC++ Linux RTOSView Embedded Software EngineerView details -
Expired
Embedded Software Engineer
@ Altera
📍New Jersey, United States 🇺🇸📊 mid-level⏱︎ full-timeC++ Linux RTOSView Embedded Software EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeC++ Verilog VHDLView FPGA Development Tools EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeSoC RTL ARMView SoC Logic Design EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeRTL FPGAs ARMView SoC Logic Design EngineerView details -
Expired
FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA C/C++ VerilogView FPGA Compiler Software EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA VLSI RTLView FPGA Circuit Design EngineerView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA IP Software Development EngineerView details -
Expired
Senior Staff FPGA Compiler Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA EDA CADView Senior Staff FPGA Compiler Software EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeC++ HLS FPGAView FPGA Development Tools EngineerView details -
Expired
Embedded Security Applications Engineer
@ Altera
📍Austin, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA Cryptography SecurityView Embedded Security Applications EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA C++ VHDLView FPGA Development Tools EngineerView details -
Expired
High Level Synthesis Compiler Intern
@ Altera
📍Toronto, Canada 🇨🇦📊 intern⏱︎ internshipC++ HLS VerilogView High Level Synthesis Compiler InternView details -
Expired
Firmware Developer
@ Altera
📍Hillsboro, OR, United States of America 🇺🇸📊 senior⏱︎ full-timeC++ FPGA RTOSView Firmware DeveloperView details -
Expired
Firmware Developer
@ Altera
📍Austin, United States 🇺🇸📊 mid-level⏱︎ full-timeC++ FPGA RTOSView Firmware DeveloperView details -
Expired
Firmware Developer
@ Altera
📍San Jose, United States 🇺🇸📊 mid-level⏱︎ full-timeC++ FPGA RTOSView Firmware DeveloperView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA IP Software Development EngineerView details -
Expired
FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA C++ SystemVerilogView FPGA Compiler Software EngineerView details -
Expired
Senior/Lead FPGA Silicon Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA RTL SoCView Senior/Lead FPGA Silicon Design EngineerView details -
Expired
Embedded Applications Engineer
@ Altera
📍Austin, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA FreeRTOS UBootView Embedded Applications EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 mid-level⏱︎ full-timeC++ Python FPGAView FPGA Development Tools EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA C++ PythonView FPGA Development Tools EngineerView details -
Expired
Principal FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 principal⏱︎ full-timeFPGA CAD optimizationView Principal FPGA Compiler Software EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeC++ DMA I2CView FPGA Development Tools EngineerView details -
Expired
Senior FPGA IP Solutions Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA RTL EDAView Senior FPGA IP Solutions EngineerView details -
Expired
Principal FPGA Compiler Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 principal⏱︎ full-timeFPGA EDA optimizationView Principal FPGA Compiler Software EngineerView details -
Expired
PD SOC EMIR Engineer
@ Altera
📍Delhi Cantonment, India 🇮🇳📊 mid-level⏱︎ full-timesynthesis routing timingView PD SOC EMIR EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Jerusalem District, Israel 🇮🇱📊 senior⏱︎ full-timelayout DRC LVSView Analog Layout Design EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Penang, India 🇮🇳📊 senior⏱︎ full-timeFPGA CMOS circuitView FPGA Circuit Design EngineerView details -
Expired
FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA Quartus C++View FPGA Compiler Software EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeRTL ARM timingView SoC Logic Design EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeRTL ARM DFTView SoC Logic Design EngineerView details -
Expired
Senior SoC Integration/Signoff Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeSoC RTL STAView Senior SoC Integration/Signoff EngineerView details -
Expired
Senior FPGA Compiler Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA optimization CADView Senior FPGA Compiler Software EngineerView details -
Expired
FPGA Software Engineer Intern
@ Altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ internshipFPGA C/C++ PythonView FPGA Software Engineer InternView details -
Expired
Senior SoC Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSoC ASIC UVMView Senior SoC Design Verification EngineerView details -
Expired
Senior Principal Embedded Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 principal⏱︎ full-timeFPGA RTOS LinuxView Senior Principal Embedded Software EngineerView details -
Expired
FPGA IP Design Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA SystemVerilog VerilogView FPGA IP Design EngineerView details -
Expired
FPGA Silicon Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA SoC UVMView FPGA Silicon Design Verification EngineerView details -
Expired
FPGA Silicon Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeverification SystemVerilog OVMView FPGA Silicon Design Verification EngineerView details -
Expired
Intern FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 internship⏱︎ internshipFPGA C/C++ VerilogView Intern FPGA Compiler Software EngineerView details -
Expired
FPGA Senior Applications Engineer
@ Altera
📍Mexico City Metropolitan Area, Mexico 🇲🇽📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA Senior Applications EngineerView details -
Expired
FPGA Software Engineer Intern
@ Altera
📍Toronto, Canada 🇨🇦📊 intern⏱︎ internshipFPGA Verilog VHDLView FPGA Software Engineer InternView details -
Expired
SoC Silicon Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeSoC RTL NoCView SoC Silicon Design EngineerView details -
Expired
FPGA IP and Software Engineering Intern
@ Altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ internshipFPGA C C++View FPGA IP and Software Engineering InternView details -
Expired
Intern FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ internshipFPGA Quartus HLSView Intern FPGA Compiler Software EngineerView details -
Expired
Internship – FPGA Software Design Engineer
@ Altera
📍Marlow, United Kingdom 🇬🇧📊 entry-level⏱︎ internshipFPGA C/C++ DevOpsView Internship – FPGA Software Design EngineerView details -
Expired
Internship – FPGA Hardware Design Engineer
@ Altera
📍Marlow, United Kingdom 🇬🇧📊 entry-level⏱︎ internshipFPGA Verilog VHDLView Internship – FPGA Hardware Design EngineerView details -
Expired
Senior/Lead FPGA Silicon Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA RTL SoCView Senior/Lead FPGA Silicon Design EngineerView details -
Expired
FPGA Silicon Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA RTL SoCView FPGA Silicon Design EngineerView details -
Expired
Graduate Talent - SOC FCT Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ contractSTA FPGA DFTView Graduate Talent - SOC FCT Design EngineerView details -
Expired
Senior Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeVerilog SystemVerilog UVMView Senior Design Verification EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeRTL Verilog SystemVerilogView SoC Logic Design EngineerView details -
Expired
FPGA IP Design Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA SystemVerilog VerilogView FPGA IP Design EngineerView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA IP MIPIView FPGA IP Software Development EngineerView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeFPGA VHDL VerilogView FPGA IP Software Development EngineerView details -
Expired
Principal FPGA Compiler Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 principal⏱︎ full-timeFPGA EDA routingView Principal FPGA Compiler Software EngineerView details -
Expired
SoC & FPGA Performance Architect
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeC++ SystemC TLM2.0View SoC & FPGA Performance ArchitectView details -
Expired
FPGA Design Applications Engineer
@ Altera
📍Austin, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA RTL VerilogView FPGA Design Applications EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeRTL SoC NoCView SoC Logic Design EngineerView details -
Expired
Senior FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA CAD EDAView Senior FPGA Compiler Software EngineerView details -
Expired
FPGA Applications Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA ASIC VerilogView FPGA Applications EngineerView details -
Expired
Senior FPGA Compiler Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA optimization algorithmsView Senior FPGA Compiler Software EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍Haifa District, Israel 🇮🇱📊 senior⏱︎ full-timelayout verification EDAView Analog Layout Design EngineerView details -
Expired
SoC & FPGA Performance Architect
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeC++ SystemC TLMView SoC & FPGA Performance ArchitectView details -
Expired
FPGA IP Design Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 mid-level⏱︎ full-timeFPGA SystemVerilog VerilogView FPGA IP Design EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeRTL ARM DFTView SoC Logic Design EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeRTL ARM DFTView SoC Logic Design EngineerView details -
Expired
FPGA Silicon Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeFPGA RTL SoCView FPGA Silicon Design EngineerView details -
Expired
FPGA Application Engineer PCIe
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA PCIe EthernetView FPGA Application Engineer PCIeView details -
Expired
FPGA Tools Developer Intern
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ internshipFPGA Quartus programmingView FPGA Tools Developer InternView details -
Expired
FPGA IP Design Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 entry-level⏱︎ full-timeFPGA SystemVerilog VerilogView FPGA IP Design EngineerView details -
Expired
RTL Design Lead Hardware Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeRTL VHDL VerilogView RTL Design Lead Hardware EngineerView details -
Expired
FPGA Application Engineer PCIe
@ Altera
📍Mexico City Metropolitan Area, Mexico 🇲🇽📊 senior⏱︎ full-timeFPGA VHDL VerilogView FPGA Application Engineer PCIeView details -
Expired
Senior FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 senior⏱︎ full-timeFPGA EDA optimizationView Senior FPGA Compiler Software EngineerView details -
Expired
Principal FPGA Compiler Software Engineer
@ Altera
📍Toronto, Canada 🇨🇦📊 principal⏱︎ full-timeFPGA optimization algorithmsView Principal FPGA Compiler Software EngineerView details -
Expired
Senior FPGA Compiler Software Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA CAD graphView Senior FPGA Compiler Software EngineerView details -
Expired
IP Silicon Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA UVM RTLView IP Silicon Design Verification EngineerView details -
Expired
Silicon Design Verification Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeFPGA SystemVerilog UVMView Silicon Design Verification EngineerView details -
Expired
Principal Engineer, IP Design Verification
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeSystemVerilog UVM emulationView Principal Engineer, IP Design VerificationView details -
Expired
SOC/FPGA Silicon Design Verification Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeUVM SystemVerilog TCLView SOC/FPGA Silicon Design Verification EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeRTL SoC AMBAView SoC Logic Design EngineerView details -
Expired
SoC and IP Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeRTL PCIe NetworkingView SoC and IP Design EngineerView details -
Expired
FPGA Pre Silicon Design Verification Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeFPGA SystemVerilog DFTView FPGA Pre Silicon Design Verification EngineerView details -
Expired
Senior SoC Embedded FPGA Application Engineer
@ Altera
📍Marlow, United Kingdom 🇬🇧📊 senior⏱︎ full-timeFPGA ARM RISC-VView Senior SoC Embedded FPGA Application EngineerView details -
Expired
FPGA Silicon Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeOVM UVM SystemVerilogView FPGA Silicon Design Verification EngineerView details -
Expired
SoC Design Verification Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeSystemVerilog UVM emulationView SoC Design Verification EngineerView details -
Expired
RISC-V Soft CPU Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeVerilog VHDL CPUView RISC-V Soft CPU Design EngineerView details -
Expired
FPGA Circuit Design Engineer
@ Altera
📍Delhi Cantonment, India 🇮🇳📊 senior⏱︎ full-timeFPGA CMOS verificationView FPGA Circuit Design EngineerView details -
Expired
FPGA Silicon Design Verification Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ full-timeSystemVerilog UVM PythonView FPGA Silicon Design Verification EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeSoC RTL NoCView SoC Logic Design EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeRTL ARM DFTView SoC Logic Design EngineerView details -
Expired
FPGA post Silicon Validation Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ contractVLSI FPGA ValidationView FPGA post Silicon Validation EngineerView details -
Expired
Senior FPGA IP Software Development Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeVHDL Verilog SystemVerilogView Senior FPGA IP Software Development EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 senior⏱︎ full-timeVerification SystemVerilog UVMView Design Verification EngineerView details -
Expired
Analog Layout Design Engineer
@ Altera
📍San Jose, United States of America 🇺🇸📊 mid-level⏱︎ full-timeanalog layout ESDView Analog Layout Design EngineerView details -
Expired
FPGA post Silicon Validation Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 mid-level⏱︎ contractFPGA VLSI ValidationView FPGA post Silicon Validation EngineerView details -
Expired
FPGA Silicon Design Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA Verilog SystemVerilogView FPGA Silicon Design EngineerView details -
Expired
FPGA Development Tools Engineer
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA C++ VHDLView FPGA Development Tools EngineerView details -
Expired
FPGA Development Tool Engineer-1
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ full-timeFPGA C++ PythonView FPGA Development Tool Engineer-1View details -
Expired
FPGA Silicon Validation Engineer
@ Altera
📍Bengaluru, India 🇮🇳📊 senior⏱︎ full-timeVLSI Verilog SystemVerilogView FPGA Silicon Validation EngineerView details -
Expired
FPGA IP Software Development Engineer
@ Altera
📍Washington, United States 🇺🇸📊 mid-level⏱︎ full-timeFPGA RTL SystemVerilogView FPGA IP Software Development EngineerView details -
Expired
Design Verification Engineer
@ Altera
📍Marlow, United Kingdom 🇬🇧📊 senior⏱︎ full-timeSystemVerilog UVM TCLView Design Verification EngineerView details -
Expired
FPGA Silicon Design Engineer
@ Altera
📍San Jose, United States 🇺🇸📊 senior⏱︎ full-timeRTL System VerilogView FPGA Silicon Design EngineerView details -
Expired
FPGA IP Software Development Engineer-Intern
@ Altera
📍California, United States 🇺🇸📊 intern⏱︎ internshipFPGA RTL DSPView FPGA IP Software Development Engineer-InternView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Austin, United States 🇺🇸📊 senior⏱︎ full-timeRTL IP ARMView SoC Logic Design EngineerView details -
Expired
SoC Logic Design Engineer
@ Altera
📍Texas, United States 🇺🇸📊 senior⏱︎ full-timeRTL ARM EthernetView SoC Logic Design EngineerView details -
Expired
Graduate Talent - FPGA IP Software Development-1
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ contractFPGA VHDL VerilogView Graduate Talent - FPGA IP Software Development-1View details -
Expired
Graduate Talent - FPGA IP Software Development
@ Altera
📍Penang, Malaysia 🇲🇾📊 entry-level⏱︎ contractFPGA VHDL VerilogView Graduate Talent - FPGA IP Software DevelopmentView details -
Expired
FPGA Development Tool Engineer-2
@ Altera
📍Penang, Malaysia 🇲🇾📊 mid-level⏱︎ full-timeFPGA C++ PythonView FPGA Development Tool Engineer-2View details
No jobs match your filters
Try adjusting your search criteria
Companies hiring in similar tech domains
Serve Robotics
18 openings
Arrow Electronics
64 openings
Waymo
37 openings
STR
32 openings
Semtech
33 openings
Aurora
20 openings
altera Job Alerts
Get notified about new altera openings and similar opportunities in embedded systems
About altera
Altera designs and manufactures FPGAs, CPLDs, and SoCs, primarily serving the telecommunications, automotive, and industrial markets. Headquartered in San Jose, California, Altera's products enable high-performance computing and signal processing applications. The engineering team focuses on digital design, hardware verification, and embedded systems development. Engineers work on optimizing FPGA architectures and developing software tools for design automation. Altera's significant presence in the FPGA market is marked by its innovative product lines and extensive customer base.
altera Career Opportunities
altera currently has 19 active embedded systems positions spanning 5 countries. All positions are on-site, typical for hardware-focused roles requiring lab access and equipment. Recognized as a top-tier employer (85.0/100), altera offers competitive compensation and strong career development paths in embedded engineering.
altera Hiring Trends
* Data represents job posting activity over the past 6 months: Jan 2026 through Jun 2026
altera's hiring pace has moderated recently (14 openings this month vs 18 last month),
which is common after major hiring pushes or as projects move from development to deployment phases.
Over the past 6 months, altera averaged 23.3 job postings per month,
with peak hiring in Mar 2026 (40 openings).
For embedded systems roles, hiring activity typically correlates with product development cycles,
especially for firmware teams during pre-production phases and hardware engineers during prototyping.
📉 -22% change
Consistent hiring velocity
Mar 2026
Required Skills at altera
FPGA is the most in-demand skill at altera,
appearing in 67% of all job listings (past and present).
This skill is important but not universal, indicating diverse technical needs across different product lines or teams.
altera's technology stack spans 196 distinct skills and tools,
reflecting the multifaceted nature of embedded systems development.
The broad technical diversity (196 technologies) suggests work on complex,
multi-domain projects requiring both hardware and software expertise.
Engineers joining altera should combine depth in key areas with adaptability. The mix of hardware skills (PCB design, schematics) and firmware expertise (RTOS, embedded C) indicates full-stack embedded development where engineers work across the hardware-software boundary. Candidates with adjacent skills (version control, testing frameworks, communication protocols) typically advance faster by contributing across the development lifecycle.
Engineering Roles at altera
altera's primary hiring focus is FPGA Engineer with
15 open positions. High-volume recruitment for a single role type typically indicates
either a growing team building similar capabilities or a newly formed department scaling rapidly.
Multiple openings in the same discipline create advantages for new hires:
stronger peer support networks, established onboarding processes, and clearer career progression paths
as the team matures. Engineers often find collaborative environments more conducive to professional growth.
Experience level distribution: 58% of openings target senior-level engineers. The range across 4 experience levels suggests a well-balanced team structure with opportunities for both experienced engineers and those earlier in their careers.
Where altera is Hiring
altera operates across 10 countries with 23
total hiring locations. Multi-geography recruitment typically indicates either distributed engineering teams,
expansion into new markets, or proximity to manufacturing and customer operations.
Penang, Malaysia serves as a primary hiring hub with 24% of all roles
(62 positions).
Engineering capabilities are distributed relatively evenly across locations, suggesting a
genuinely multi-site development model rather than a single headquarters-centric approach.
Companies Similar to altera
These employers share technical focus areas with altera and are actively hiring embedded engineers. Exploring multiple companies helps candidates understand market compensation, compare technical challenges, and identify the best cultural and technical fit for their career goals.
Create Job Alert for altera 📬
Get instant updates when altera posts new embedded systems positions.
Free forever • No credit card • 2000+ engineers signed up