RISC-V Soft CPU Design Engineer

Job Details

Job Description:

For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.

Join us in our journey to becoming the #1 FPGA company!

We are hiring talented engineer for CPU RTL development targeted for high performance & Altera FPGA devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with CPU architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.

Roles And Responsibilities

• Performance exploration. Explore high performance strategies working with the CPU Architect team.
• Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.
• RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Functional verification support. Help the design verification team execute on the functional verification strategy.
• Performance verification support. Help verify that the RTL design meets the performance goals.
• Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability .
  
  

Salary Range

$128,900 - $186,650 USD

Qualifications

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering (or related experience).
  
  

Preferred Qualifications

• Microprocessor architecture including experience in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems
• Verilog and/or VHDL
• Experience with simulators and waveform debugging tools
• Logic design principles along with timing and FPGA resource implications
• High performance techniques and trade-offs in a CPU microarchitecture
• Scripting language (e.g., Perl or Python)
  
  

Job Type

Regular

Shift

Shift 1 (United States of America)

Primary Location:

San Jose

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.