Job Details
Job Description:
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Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
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Participates in the definition of architecture and microarchitecture features of the block being designed.
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Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
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Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
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Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IP-SoC handoff.
Qualifications
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Bachelor’s Degree in electrical/computer engineering or related field and 2+ years of experience Or a master’s degree in electrical/computer engineering or related field. 2+ years of RTL coding and/or IP integration experience into SoC design. Experience in design related tools such as LINT, CDC, PT-STA, Fishtail, Power UPF etc & design concept such as data flow, algorithm state machine, finite state machines, and timing charts. Knowledge on FPGA background would be a plus. Highly motivated individual, team player with good communication skill.
Job Type
Regular
Shift
Shift 1 (Malaysia)
Primary Location:
Penang 15, Penang, Malaysia
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.