Design Verification Engineer

Job Details

Job Description:

About Altera

For decades, Altera has been at the forefront of programmable logic technology, delivering industry-leading FPGA, SoC FPGA, and heterogeneous computing solutions. Our technologies enable customers across data center, automotive, aerospace & defense, communications, and industrial markets to solve some of the world’s most complex engineering challenges. At Altera, we foster a culture of innovation, technical excellence, and collaboration while building products that shape the future of computing.

About The Role

Altera is seeking a Senior Design Verification Engineer to drive verification of complex FPGA and SoC designs from architecture through silicon validation. This role is a highly technical, hands-on position for an experienced verification engineer who will own verification strategy for major blocks or full subsystems, influence design quality, and serve as a technical leader within the verification community.

Responsibilities

• Own and execute design verification for complex FPGA and SoC blocks and subsystems
• Develop verification plans, testbenches, checkers, and coverage models
• Drive verification methodology using SystemVerilog, UVM, constrained-random testing, and assertions
• Analyze functional coverage, identify verification gaps, and ensure thorough sign-off
• Collaborate closely with Design, Architecture, and Emulation teams to influence microarchitecture and design quality
• Debug complex RTL and system-level issues across simulation, emulation, and post-silicon environments
• Contribute to verification infrastructure, automation, and reusable VIP development
• Mentor junior verification engineers through technical guidance and code reviews
• Support silicon bring-up and correlation between pre-silicon and post-silicon results
  
  

Qualifications

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
• 12+ years of Design Verification experience in complex ASIC, SoC, or FPGA environments
• Strong expertise in SystemVerilog, UVM, constrained-random verification, and functional coverage
• Proven experience verifying large-scale digital designs and IPs
• Solid understanding of digital design, microarchitecture, and system-level integration
• Experience debugging complex functional and performance issues in RTL designs
  
  

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field
• Experience with formal verification, emulation, and acceleration platforms
• Background in FPGA or SoC FPGA architectures
• Familiarity with power-aware verification and low-power methodologies
• Experience developing reusable verification IP and frameworks
• Demonstrated ability to influence technical direction without formal people management
  
  

Job Type

Contract Employee (Fixed Term)

Shift

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.