FPGA Post Silicon Validation Engineer

Job Details

Job Description:

About The Role

Join our high‑performance Silicon Validation team and play a key role in enabling next‑generation high‑speed FPGA/PLD devices with a strong focus on PCIe Gen 4, PCIe Gen 5, and future‑generation PCIe technologies. You will drive device‑level and PCIe Digital IP validation, platform development, and infrastructure enablement to ensure industry‑leading quality, reliability, and performance. This role provides the opportunity to work hands‑on with advanced high‑speed serial interfaces, collaborate across multiple engineering teams, and influence the architecture of future PCIe‑enabled FPGA products.

Key Responsibilities

• Develop comprehensive validation strategies for high‑speed FPGA devices and PCIe Gen4/Gen5 and future PCIe Digital IP, aligning with technical, architectural, and business requirements.
• Create and generate test patterns and vectors for device‑level and PCIe protocol characterization, including link training, LTSSM behaviour, equalization, bandwidth analysis, and interoperability testing.
• Utilize industry‑leading Protocol Exerciser/Analyzer solutions for PCIe protocol validation, traffic generation, error injection, and trace analysis.
• Work with a broad range of test cards and IHV platforms to perform interoperability validation using both internal and industry‑standard PCIe‑compliant devices.
• Perform PCIe link bring‑up, compliance pre‑checks, and performance validation across PCIe Gen4, Gen5, and next‑generation specifications.
• Drive innovation in validation methodologies, automation flows, test platforms, and infrastructure to enhance scalability, efficiency, and throughput for future PCIe generations.
• Collaborate on high‑speed PCB design, contributing to PCIe Gen4/Gen5‑ready and next‑generation PCIe evaluation boards for device, platform, and IP validation.
  
  

Qualifications

• Bachelor’s / master’s degree in electrical & Electronics Engineering (BSEEE) or related field.
• 8+ years of hands-on experience in PCIe silicon validation methodology, test planning, test development and debug
• Solid understanding of FPGA validation methodologies with hands‑on experience in system validation and debug
• Knowledge of PCIe Gen4/Gen5 protocol, including LTSSM, link training, equalization, protocol compliance, and high‑speed serial signalling; familiarity with next‑generation PCIe standards is a strong advantage.
• Knowledge of FPGA architecture (advantage).
• Experience or familiarity with programming languages such as Python and Verilog (plus).
  
  

Job Type

Regular

Shift

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.