FPGA SW Validation Engineer - Sr./Lead

• Validates and researches the Compiler optimizations, Partial Reconfiguration ( PR ) flow, Debugging features like SignalTap & System Console, etc. using
• Quartus Design Software and Altera FPGA Hardware.
• Leads the Partial Reconfiguration (PR) Validation team
• Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA Hardware Boards.
• Regresses the designs during each release for QoR, and monitors performance over the targeted FPGA devkits to assess improvements.
• Collaborates with cross-functional teams to develop and improve validation strategies for improving Compiler/PR validation and help resolve customer issues as they occur.
• Experience : 6+ years of relevant experience in FPGA/ASIC Design, verification and HW Debug
• Education : Master's/Bachelor's Degree in Electronics/VLSI/Digital Design or other related disciplines

Requirement s

• - FPG A/Digital Logic Design, RTL design and verification using VHDL, Verilog or SystemVerilo g
• .Experienced in FPGA Devices like Agile x, Virtex and Tools like Altera Quartu s, Xilinx Vivado, Synplify, et
• cGood experience in FPGA Partial Reconfiguration (PR) flow, and HW debugging skill s using SignalTap or ChipScop
• eGood experience with Simulation/Verificatio n of digital designs using VCS, Questa, XCelium, STA and Hardware validation of FPGA Design
• sKnowledge of Shell, Perl/TCL or Python Scripting is require
• dKnowledge of AHB, AX I, PCI e, Ethernet, Avalon bus protocols, and High-Speed interfaces is essentia