Design Verification Engineer

Job Requirements

POSITION: Lead DV Engineer

Who We Are

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

What You Will Do

• As a verification engineer with a knowledge of subsystems and SoCs, you will make valuable contributions to a team tasked with verifying the functional correctness of SoC.
• Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy.
• Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules.
• Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level.
• Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development.
  
  

What You Will Bring

• Experience in block/IP/sub-system level verification of SoC IPs/ Peripherals; experience in ARM based boot environment preferred
• knowledge of ARM architecture and AMBA bus standards like AXI-4
• Experience with industry standard interfaces such as PCIe (preferably gen6), NVMe 2.0
• Experience in coding UVM SOC/ Subsys level test benches, BFM, scoreboards, monitors etc
• Proficient in writing and debugging tests in UVM as well as C
  
  

Work Experience

Educational Qualification : Bachelor’s degree / MS or PHD in Electrical Engineering with 10+ Years of Experience

Pay Range: $120,000 K - $190,000K

Work Requirements

This role is considered an on-site position located in Santa Clara, California

• You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.