SOC Design Verification Engineer

(1.)Design Verification Engineer (Performance Modelling) – Sunnyvale CA or Austin TX

We need a DV engineer for our Client who has performance validation experience.

Key Responsibilities

• Develop, maintain, and enhance STL (Scenario/Test List) generation scripts and performance validation infrastructure.

• Monitor performance regression status and track key performance indicators (KPIs) across IP and subsystem level verification environments.

• Analyze regression failures and collaborate with IP, Design, and DV owners to drive issue resolution.

• Debug verification tests that fail to meet defined performance metrics and benchmark targets.

• Create, maintain, and update performance test plans, validation dashboards, and result tracking reports.

• Develop and execute SystemVerilog/UVM-based testcases and regression suites.

• Drive verification closure through regression analysis, debugging, and coverage tracking.

• Automate validation and reporting workflows using Python, Perl, or Shell scripting.

• Work closely with architects, designers, software teams, and validation engineers to ensure feature and performance signoff.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 5+ years of Design Verification experience.

• Strong expertise in SystemVerilog and UVM.

• Experience developing and maintaining verification testbenches and regression environments.

• Strong debugging and root-cause analysis skills.

• Experience with verification planning, test development, and coverage closure.

• Proficiency in Python, Perl, or Shell scripting.

• Experience using industry-standard simulators and debug tools such as VCS, Xcelium, Questa, Verdi, or equivalent.

Preferred Qualifications

• Experience with performance validation, KPI tracking, or performance regression analysis.

• Experience with CPU, GPU, AI/ML, Multimedia, Interconnect, or SoC verification.

• Familiarity with performance benchmarking methodologies.

• Experience with emulation, FPGA prototyping, or post-silicon validation environments.

• Exposure to Formal Verification methodologies is a plus.

Key Skills

• SystemVerilog

• UVM

• Python / Perl / Shell

• Regression Debugging

• Verification Planning

• Coverage Analysis

• Performance Validation

• KPI Tracking

• Root Cause Analysis

• SoC/IP Verification

Tasks to be Owned

• Own and maintain healthy performance regression suites.

• Ensure performance KPIs are continuously tracked and reported.

• Drive timely debug and closure of performance-related test failures.

• Maintain accurate and up-to-date performance validation plans and dashboards.

• Partner effectively with cross-functional teams to achieve verification and performance signoff.

(2.)Design Verification Engineer (AI) – Austin TX

We need a DV engineer for our Client who has AI experience.

The ideal candidate for our AI-based HW IP / SoC development SPW would:

Have a good understanding of AI-based HW IP / SoC development.

Be on the forefront of general AI trends (e.g., understanding of various LLMs and their relative strengths/weaknesses based on application).

Have a baseline understanding of DV, including key measurements (e.g., coverage metrics).

Key Responsibilities:

Strong understanding of SV and UVM and good debugging skills.

Understanding of AMBA protocols.

Understand design specs and develop test plans based on functional and architectural requirements

Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing

Develop directed and random testcases, perform coverage analysis, and close functional/code coverage

Debug simulation failures and work closely with RTL designers to resolve issues

Execute regression runs, analyze results, and contribute to continuous improvements

Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed

Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains

Document test environments, testplans, and results for internal and external reviews