Design Verification Engineer
Quest Global ↗
📍 Vietnam, Vietnam 🇻🇳
full-time
mid-level
Expired
Posted —
This job posting has expired
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Key Skills
VerilogSystemVerilogUVMPCIEAXI
Industry
SemiconductorAerospace
Job Description
Job Requirements
Responsible for Verification from Verification Strategy, Testbench Development, Verification Item List to Simulation, Coverage Analysis.
Responsible for Verification from Verification Strategy, Testbench Development, Verification Item List to Simulation, Coverage Analysis.
- Verification Strategy/Test Plan Development: Create Strategy/Plan based on Design specification/Micro Architecture.
- Testbench Development, Simulation/Debugging to identify and resolve any issues/failures of the design.
- Work closely with Synthesis/PD teams to address any defects in Netlist, Timing SDF and ensure specifications are met.
- Coverage analysis to detect uncovered areas that need further testing.
-
Documentation and reporting for progress tracking, detailed feedback to design teams, verification result.
- Good Experience on SoC/Sub-System/IP level verification
- Experience in Verilog/System-Verilog/VHDL/C
- Experience in UVM/Arm-based environment
- Experience in Gate Level Simulation (Zero-delay/Timing SDF)
- Good knowledge on Bus protocols AXI/APB/AHB
- Experience in PCIE, DDR, USB, UCIE is a plus
- Familiar with simulation and debugging tools VCS/DVE/Verdi/Xcelium/Simvision
- Familiar with scripting languages (Python, Perl, Shell, Tcl)
- Good on Debugging/Problem Analyzing
- Perl/python scripting
- Fluent English both in writing and speaking
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Key Skills
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