Job Title:
Design Verification Engineer
Location:
CA
Experience Level:
10+ Years
Job Description:
We are seeking a skilled
Design Verification Engineer
with strong expertise in
System Verilog (SV)
and
UVM
methodologies to join our team. The ideal candidate will have hands-on experience in developing, updating, and debugging
verification testbenches
, with the ability to integrate
Verification IPs (VIPs)
or
Design IPs
into the verification environment.
Responsibilities:
-
Develop, enhance, and debug System Verilog/UVM-based testbenches for complex designs.
-
Integrate VIP/IP components and ensure smooth functionality within the verification environment.
-
Mentor team members and support cross-functional verification activities.
-
Collaborate with design engineers to understand specifications and create robust verification plans.
-
Perform simulation, debug failures, and implement fixes effectively.
Required Skills:
-
Strong proficiency in
System Verilog
and
UVM
.
-
Hands-on experience in
updating and debugging verification testbenches
.
-
Excellent problem-solving and analytical skills.
-
Strong verbal and written communication skills for effective team collaboration.
Preferred Skills (a plus):
-
Experience with
C-based testbenches
.
-
Experience integrating
VIP/IPs
.
-
Proficiency in scripting languages such as
Perl, Python, or TCL
for automation.
Education:
-
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Ready to Apply? Send us your resume and a brief intro to
[email protected]