Key Skills
SystemVerilogUVMEDAPythonGit
Industry
SemiconductorConsumer Electronics
Job Description
As a Design Verification Engineer at Meta, you will be part of a dynamic team working with the best in the industry to develop innovative ASIC solutions for data center applications and wearables. You will be responsible for the verification closure of design modules or sub-systems from test-planning, UVM-based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve bug-free designs.
Responsibilities
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality through defined verification metrics and coverage goals
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 8+ years of experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification
- Experience in IP/sub-system and/or SoC (System on Chip) level verification based on SystemVerilog UVM and OVM (Open Verification Methodology) based methodologies
- Experience in one or more of the following areas along with functional verification - System Verilog Assertions, Formal, Emulation
- Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Track record of 'first-pass success' in ASIC (Application-Specific Integrated Circuit) development cycles
Preferred Qualifications
- Experience with revision control systems like Mercurial, Git or SVN
- Experience working across and building relationships with cross-functional design, model and emulation teams
- 12+ years of experience in development of UVM based verification environments from scratch
- Experience with verification of ARM/RISC-V based sub-systems or SoC (Systems on Chip)
- Experience with Design verification of Data-center applications like Video, Artificial Intelligence/Machine Learning (AI/ML) and Networking designs
- Experience with IP or integration verification of high-speed interfaces like AMBA, PCIe (Peripheral Component Interconnect Express), DDR (Double Data Rate), Ethernet
- Experience in IP, sub-system and SoC level verification using SystemVerilog, UVM
Featured Opportunities
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Key Skills
SystemVerilogUVMEDAPythonGit
Industry
SemiconductorConsumer Electronics
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