2026 Campus - SoC DFT Engineer
๐Tianjin, China ๐จ๐ณ
โฑ๏ธ full-time
๐งโโ๏ธ entry-level
Responsibility
- Proficiency in whole DFT architecture definition.
- Setup and maintain DFT flow, familiar with script language.
- Be responsible for definition and implementation different schemes of DFT aspects: including scan/MBIST/JTAG insertion, ATPG generation, test patterns generation.
- Experience RTL/netlist simulation, good debug capability, familiar with Verilog.
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Experience with ATE on-line debugging and DFT diagnosis. Experience with Post-silicon DPPM improvement, coverage hole analysis.
- Bachelor or masterโs degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines.
- Good knowledge and experience in DFT implementation methodology, flow optimization and DFT coverage improvement. Mentor tool is a plus.
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Strong skills of solving problem, self-motivated and good team player.
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Employment
โฑ๏ธ full-time
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Experience
๐งโโ๏ธ entry-level
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Skills
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Industry
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