SoC Design Verification Engineer

BOS Semiconductors โ†—

๐Ÿ“ Gyeonggi, South Korea, South Korea ๐Ÿ‡ฐ๐Ÿ‡ท

full-time
mid-level
Expired
Posted โ€”
This job posting has expired View All SoC Design Engineer Jobs

Key Skills

UVMVerilogSystemVerilogsimulationemulation

Industry

SemiconductorTelecommunications

Job Description

์ž์œจ์ฃผํ–‰ ์ž๋™์ฐจ, ์–ด๋””๊นŒ์ง€ ์ƒ์ƒํ•ด ๋ณด์…จ๋‚˜์š”? ์šด์ „๋Œ€ ์—†๋Š” ์ž๋™์ฐจ. ์šด์ „์ž ์—†์ด ์•„์ด๋ฅผ ํ”ฝ์—…ํ•˜๊ณ  ๋ถ€๋ชจ๋‹˜์˜ ๊ฐ•๋ณ€ ๋“œ๋ผ์ด๋ธŒ๋ฅผ ๊ฐ€๋Šฅํ•˜๊ฒŒ ํ•˜๋Š” ์ž๋™์ฐจ.

์šฐ๋ฆฌ์˜ ์ฆ๊ฑฐ์šด ์ƒ์ƒ์ด ์ตœ์ƒ์˜ ํŽธ์•ˆํ•จ๊ณผ ํ–‰๋ณตํ•œ ์ˆœ๊ฐ„์ด ๋˜๋„๋ก ์„ธ๊ณ„์ˆ˜์ค€์˜ ์ „๋ฌธ๊ฐ€ ๊ทธ๋ฃน ใˆœ ๋ณด์Šค๋ฐ˜๋„์ฒด๊ฐ€ ๋ชจ๋นŒ๋ฆฌํ‹ฐ ํ˜์‹ ์„ ์„ ๋„ํ•˜๊ฒ ์Šต๋‹ˆ๋‹ค.


โ–ก ํšŒ์‚ฌ ์†Œ๊ฐœ

- ๋ณด์Šค๋ฐ˜๋„์ฒด(BOS Semiconductors)๋Š” ์ฐจ๋Ÿ‰์šฉ ์ž์œจ์ฃผํ–‰ ๋ฐ ์ธํฌํ…Œ์ธ๋จผํŠธ ์‹œ์Šคํ…œ์„ ์œ„ํ•œ

๊ณ ์„ฑ๋Šฅ ๋ฐ˜๋„์ฒด ๋ฐ AI ๊ฐ€์†๊ธฐ ๋ฐ˜๋„์ฒด๋ฅผ ๊ฐœ๋ฐœํ•˜๋Š” ํŒน๋ฆฌ์Šค ๊ธฐ์—…์œผ๋กœ, ์ž๋™์ฐจ๋ฅผ ์ฃผ์š” ํƒ€๊นƒ

์‹œ์žฅ์œผ๋กœ ํ•˜๋ฉฐ ๋™์ผํ•œ ์ œํ’ˆ ํ”Œ๋žซํผ์„ ๊ธฐ๋ฐ˜์œผ๋กœ ๋กœ๋ด‡ ๋“ฑ ๋‹ค๋ฅธ Physical AI ์‹œ์žฅ์œผ๋กœ์˜

ํ™•์žฅ์„ ์ถ”์ง„ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

- ๋Œ€ํ‘œ ์ œํ’ˆ์ธ Eagle-N (AI ๊ฐ€์†๊ธฐ)๊ณผ Eagle-A (์ฐจ๋Ÿ‰์šฉ SoC)๋Š” ์นฉ๋ › ๊ธฐ๋ฐ˜ ํ™•์žฅ์„ฑ๊ณผ

์„ ๋‹จ ๊ณต์ • ๊ธฐ์ˆ ์„ ๋ฐ”ํƒ•์œผ๋กœ ์ฐจ์„ธ๋Œ€ ์ฐจ๋Ÿ‰ ์ „์žฅ ๋ฐ ์ง€๋Šฅํ˜• ์‹œ์Šคํ…œ์— ์ตœ์ ํ™”๋œ ์„ฑ๋Šฅ๊ณผ ์ „๋ ฅ

ํšจ์œจ์„ ์ œ๊ณตํ•ฉ๋‹ˆ๋‹ค.

-ย ์ฐฝ์—… 4๋…„ ์ฐจ์ธ ๋ณด์Šค๋ฐ˜๋„์ฒด๋Š” 300๋ช… ์ด์ƒ์˜ ์—ฐ๊ตฌ๊ฐœ๋ฐœ์ธ๋ ฅ๊ณผ ๋ฒ ํŠธ๋‚จR&D ๋ฒ•์ธ์„ ๊ธฐ๋ฐ˜์œผ๋กœ,

์ฐจ๋Ÿ‰์šฉ ๊ณ ์„ฑ๋Šฅ ๋ฐ˜๋„์ฒด๋ฅผ ์ž์ฒด ๊ฐœ๋ฐœํ•˜์—ฌ ์ƒ˜ํ”Œ ์ถœ์‹œ๊นŒ์ง€ ์„ฑ๊ณต์ ์œผ๋กœ ๋งˆ์ณค์œผ๋ฉฐ ๊ณ„์†ํ•ด์„œ ๋น ๋ฅด๊ฒŒ

์„ฑ์žฅํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค. Global Top ๊ธฐ์ˆ ๋ ฅ์„ ๊ฐ€์ง„ ๊ธฐ์—…๋“ค๊ณผ ๊ฒฝ์Ÿํ•˜๋ฉฐ ์˜๋ฏธ ์žˆ๋Š” ์„ฑ์žฅ์„ ํ•จ๊ป˜

๋งŒ๋“ค์–ด๊ฐˆ ์ธ์žฌ๋ฅผ ๋ชจ์ง‘ํ•ฉ๋‹ˆ๋‹ค.

โ–ก ์กฐ์ง ๋ฐ ์—…๋ฌด ์†Œ๊ฐœ

- ๋ณด์Šค๋ฐ˜๋„์ฒด์˜ SOC ๊ฒ€์ฆํŒ€์€ ์ž์œจ์ฃผํ–‰ SoC๋ฅผ ๋น„๋กฏํ•œ ์—ฌ๋Ÿฌ SoC ์ œํ’ˆ์˜ ์„ค๊ณ„๊ฒ€์ฆ์„ ์—…๋ฌด๋ฅผ

์ˆ˜ํ–‰ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

- ์ •์˜๋œ specification์„ ๋ฐ”ํƒ•์œผ๋กœ ์„ค๊ณ„๊ฐ€ ์˜๋„๋Œ€๋กœ ๊ตฌํ˜„๋˜์–ด ์žˆ๋Š”์ง€๋ฅผ ๊ธฐ๋Šฅ๋ฉด, ์„ฑ๋Šฅ๋ฉด, ํŒŒ์›Œ๋ฉด,

timing๋ฉด, ๊ธฐ๋Šฅ์•ˆ์ „๋ฉด ๋“ฑ์—์„œ ๊ฒ€์ฆ์„ ์ง„ํ–‰ํ•˜๊ณ  ์žˆ์œผ๋ฉฐ, ํ˜„์žฌ ์—…๊ณ„์—์„œ ์‚ฌ์šฉ๋˜๊ณ  ์žˆ๋Š” ๊ฐ€์žฅ ๋†’์€

์ˆ˜์ค€์˜ state-of-art ๊ธฐ์ˆ ์„ ์ฑ„ํƒํ•˜์—ฌ ๊ฒ€์ฆ์„ ์ง„ํ–‰ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

โ–ก ์ฃผ์š” ์—…๋ฌด

- UVM (Universal Verification Methodology)๋ฅผ ์‚ฌ์šฉํ•œ IP/block ์ˆ˜์ค€, SoC ์ˆ˜์ค€์—์„œ์˜ ๊ธฐ๋Šฅ ๊ฒ€์ฆ

- MDV (Metric Driven Verification) ๋ฐฉ๋ฒ•๋ก ์„ ์ด์šฉํ•œ verification closure

- Testbench architecting ๋ฐ verification environment ๊ตฌ์„ฑ ์š”์†Œ ๊ตฌํ˜„

- ABV (Assertion Based Verification) ๊ธฐ๋ฐ˜์˜ ๊ฒ€์ฆ

- Simulation, emulation, FV (Formal Verification) ๊ธฐ๋ฐ˜์˜ ๊ฒ€์ฆ ๋ฐฉ๋ฒ•๋ก 

- Advanced simulation: Power-aware, X-propagation, and meta-injection simulation

โ–ก ํ•„์š” ์—ญ๋Ÿ‰

- ์ปดํ“จํ„ฐ๊ณตํ•™, ์ „๊ธฐ์ „์ž๊ณตํ•™ ์ „๊ณต ํ•™์‚ฌ ์ด์ƒ

- Verilog ํ˜น์€ SystemVerilog ์–ธ์–ด์— ๋Œ€ํ•œ ์ดํ•ด ๋ฐ ์‹ค๋ฌด ๊ฒฝํ—˜

- Project ํŒ€์˜ ์ผ์›์œผ๋กœ ํƒ€์ธ๊ณผ ํ˜‘์—…์„ ํ†ตํ•ด ์—…๋ฌด ์ˆ˜ํ–‰ ๊ฐ€๋Šฅํ•˜์‹  ๋ถ„

- ๋ฐ˜๋„์ฒด, ์ปดํ“จํ„ฐ ๊ตฌ์กฐ, ๋กœ์ง์„ค๊ณ„์— ๋Œ€ํ•œ background

- ํ•ด์™ธ ์—ฌํ–‰์— ๊ฒฐ๊ฒฉ ์‚ฌ์œ ๊ฐ€ ์—†์œผ์‹  ๋ถ„

โ–ก ์šฐ๋Œ€ ์‚ฌํ•ญ

- UVM ๊ธฐ๋ฐ˜์˜ ์„ค๊ณ„๊ฒ€์ฆ ๊ฒฝํ—˜์ž

- ์›ํ™œํ•œ ์˜์–ด ์†Œํ†ต(speaking ์œ„์ฃผ)์„ ํ†ตํ•ด ์™ธ๊ตญ์ธ๊ณผ ํ˜‘์—… ๊ฐ€๋Šฅํ•˜์‹  ๋ถ„

- ์—…๋ฌด ๋ชฉํ‘œ๋ฅผ ๋ฐ”ํƒ•์œผ๋กœ ์ •ํ•ด์ง„ ๊ธฐํ•œ๋‚ด์— ์ฃผ์–ด์ง„ ๋ชฉํ‘œ๋ฅผ ๋‹ฌ์„ฑํ•  ์ˆ˜ ์žˆ๋Š” ์‹คํ–‰๋ ฅ ์žˆ์œผ์‹  ๋ถ„

- ์ƒˆ๋กœ์šด ๋ฐฉ๋ฒ•๋ก ์„ ๋ฐ›์•„๋“ค์ด๊ณ  ๋ณ€ํ™”์™€ ํ˜์‹ ์„ ํ†ตํ•ด ์—…๋ฌด ๊ฐœ์„ ์„ ํ•  ์ˆ˜ ์žˆ์œผ์‹  ๋ถ„