Senior FPGA Engineer

Experience: 6–8 Years

✅ ASIC-to-FPGA conversion using Xilinx Vivado

✅ Verilog/SystemVerilog

✅ RTL Synthesis, Place & Route, Timing Closure & STA

✅ UltraScale/UltraScale+ FPGA devices

✅ FPGA Board Bring-up & Debug (ILA, VIO, Hardware Manager)

✅ CDC verification & XDC Constraints

✅ AXI, APB, AHB, SPI, UART & I2C protocols

✅ TCL, Python & Shell scripting for automation

• Convert ASIC/SoC RTL designs into FPGA implementations.
• Perform synthesis, implementation, place & route, and bitstream generation.
• Resolve timing closure and implementation challenges.
• Support FPGA board bring-up, hardware debugging, and functional validation.
• Collaborate with RTL, Design Verification, Firmware, and System Validation teams.
• Develop automation scripts and FPGA build flows using Vivado.

📩 Interested candidates, please share your updated resume to: [email protected]