Senior Design Verification Engineer

About Opportunity:

Scaledge is looking for experienced, talented Engineers (ASIC/IP/SOC/CPU/GLS) for dynamic and innovative Team. As a member of the team, you will be responsible for verifying the design, architecture and micro-architecture using advanced verification methodologies

Required Skills

• Strong knowledge of Verilog, System Verilog, and Object-Oriented Programming
• Experience with modern verification techniques, especially including System Verilog, UVM, constraint-random and functional coverage methodologies
• Complete understanding of verification life cycle and ability to create of comprehensive verification plans
• Knowledge of high-speed PCIe, Ethernet, DDR, USB, AXI, APB, AHB protocols
• Experience verifying networking protocols such as Ethernet is a plus
• Experience with scripting languages such as Python, Tcl, or Perl
• Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
• Strong technical writing and verbal communication skills

Education

• BTech/MTech in Electronic/Microelectronics, Electrical Engineering or Computer Science.

Other Science graduates would be considered if they have relevant experience

Interested candidate can share CV on [email protected] or DM me