Senior Design Verification Engineer

Job Summary:

We are seeking a highly skilled Verification Engineer with extensive experience in SystemVerilog and UVM methodologies. The ideal candidate will have a strong background in SoC-level verification, debugging firmware and RTL, and developing automated verification workflows in complex compute environments.

Key Responsibilities:

• Perform SoC-level verification using SystemVerilog and UVM methodologies.
• Develop and enhance UVM-based verification frameworks, testbenches, and processes.
• Debug firmware and RTL code using industry-standard simulation tools.
• Automate verification workflows in distributed compute environments to improve efficiency.
• Collaborate with cross-functional teams to ensure design quality and performance.
• Work on simulation profiling, performance optimization, and acceleration activities.
• Contribute to HLS (High-Level Synthesis) tool and process improvements.
• Ensure high verification coverage and maintain comprehensive documentation.

Required Skills & Experience:

• 8+ years of experience as a Verification Engineer.
• Strong proficiency in SystemVerilog and UVM concepts.
• Hands-on experience with Verilog, C/C++, and scripting languages (Perl/Python).
• Proficient in working across Linux and Windows environments.
• Solid understanding of graphics pipelines and related verification flows.
• Experience with simulation profiling, efficiency improvement, and acceleration techniques.
• Demonstrated ability to debug complex RTL and firmware interactions.

Preferred Qualifications:

• Experience in automation frameworks or verification efficiency initiatives.
• Exposure to HLS tools and processes.
• Familiarity with large-scale SoC verification environments