SOC RTL Design Engineer

BOS Semiconductors โ†—

๐Ÿ“ Seongnam, Gyeonggi, South Korea, South Korea ๐Ÿ‡ฐ๐Ÿ‡ท

full-time
mid-level
Expired
Posted โ€”
This job posting has expired View All SoC Design Engineer Jobs

Key Skills

RTLVerilogSystemVerilogSoCEDA

Industry

SemiconductorAutomotive

Job Description

โ–ก ํšŒ์‚ฌ ์†Œ๊ฐœ

- ๋ณด์Šค๋ฐ˜๋„์ฒด(BOS Semiconductors)๋Š” ์ฐจ๋Ÿ‰์šฉ ์ž์œจ์ฃผํ–‰ ๋ฐ ์ธํฌํ…Œ์ธ๋จผํŠธ ์‹œ์Šคํ…œ์„ ์œ„ํ•œ

๊ณ ์„ฑ๋Šฅ ๋ฐ˜๋„์ฒด ๋ฐ AI ๊ฐ€์†๊ธฐ ๋ฐ˜๋„์ฒด๋ฅผ ๊ฐœ๋ฐœํ•˜๋Š” ํŒน๋ฆฌ์Šค ๊ธฐ์—…์œผ๋กœ, ์ž๋™์ฐจ๋ฅผ ์ฃผ์š” ํƒ€๊นƒ

์‹œ์žฅ์œผ๋กœ ํ•˜๋ฉฐ ๋™์ผํ•œ ์ œํ’ˆ ํ”Œ๋žซํผ์„ ๊ธฐ๋ฐ˜์œผ๋กœ ๋กœ๋ด‡ ๋“ฑ ๋‹ค๋ฅธ Physical AI ์‹œ์žฅ์œผ๋กœ์˜

ํ™•์žฅ์„ ์ถ”์ง„ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

- ๋Œ€ํ‘œ ์ œํ’ˆ์ธ Eagle-N (AI ๊ฐ€์†๊ธฐ)๊ณผ Eagle-A (์ฐจ๋Ÿ‰์šฉ SoC)๋Š” ์นฉ๋ › ๊ธฐ๋ฐ˜ ํ™•์žฅ์„ฑ๊ณผ

์„ ๋‹จ ๊ณต์ • ๊ธฐ์ˆ ์„ ๋ฐ”ํƒ•์œผ๋กœ ์ฐจ์„ธ๋Œ€ ์ฐจ๋Ÿ‰ ์ „์žฅ ๋ฐ ์ง€๋Šฅํ˜• ์‹œ์Šคํ…œ์— ์ตœ์ ํ™”๋œ ์„ฑ๋Šฅ๊ณผ ์ „๋ ฅ ํšจ์œจ์„ ์ œ๊ณตํ•ฉ๋‹ˆ๋‹ค.

-ย ์ฐฝ์—… 4๋…„ ์ฐจ์ธ ๋ณด์Šค๋ฐ˜๋„์ฒด๋Š” 300๋ช… ์ด์ƒ์˜ ์—ฐ๊ตฌ๊ฐœ๋ฐœ์ธ๋ ฅ๊ณผ ๋ฒ ํŠธ๋‚จR&D ๋ฒ•์ธ์„ ๊ธฐ๋ฐ˜์œผ๋กœ,

์ฐจ๋Ÿ‰์šฉ ๊ณ ์„ฑ๋Šฅ ๋ฐ˜๋„์ฒด๋ฅผ ์ž์ฒด ๊ฐœ๋ฐœํ•˜์—ฌ ์ƒ˜ํ”Œ ์ถœ์‹œ๊นŒ์ง€ ์„ฑ๊ณต์ ์œผ๋กœ ๋งˆ์ณค์œผ๋ฉฐ ๊ณ„์†ํ•ด์„œ ๋น ๋ฅด๊ฒŒ

์„ฑ์žฅํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค. Global Top ๊ธฐ์ˆ ๋ ฅ์„ ๊ฐ€์ง„ ๊ธฐ์—…๋“ค๊ณผ ๊ฒฝ์Ÿํ•˜๋ฉฐ ์˜๋ฏธ ์žˆ๋Š” ์„ฑ์žฅ์„ ํ•จ๊ป˜

๋งŒ๋“ค์–ด๊ฐˆ ์ธ์žฌ๋ฅผ ๋ชจ์ง‘ํ•ฉ๋‹ˆ๋‹ค.


โ–ก ์กฐ์ง ๋ฐ ์—…๋ฌด ์†Œ๊ฐœ

- SoC DesignํŒ€์€ ์ž์œจ์ฃผํ–‰์šฉ SoC๋ฅผ ํฌํ•จํ•œ ๋‹ค์–‘ํ•œ ๋ฐ˜๋„์ฒด ์ œํ’ˆ์˜ ์„ค๊ณ„๋ฅผ ์ˆ˜ํ–‰ํ•˜๋ฉฐ, ์—…๊ณ„ ์ตœ๊ณ 

์ˆ˜์ค€์˜ ์ตœ์‹  ๊ธฐ์ˆ (state-of-the-art)์„ ์ ๊ทน์ ์œผ๋กœ ์ ์šฉํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค. 3rd-party IP์™€ in-house IP๋ฅผ

๊ธฐ๋ฐ˜์œผ๋กœ ๊ธฐ๋Šฅ ๊ตฌํ˜„์€ ๋ฌผ๋ก , PPA(Power, Performance, Area) ์ตœ์ ํ™”๋ฅผ ๋™์‹œ์— ๋‹ฌ์„ฑํ•˜๋Š” ์•„ํ‚คํ…์ฒ˜

์„ค๊ณ„๋ฅผ ์ง€ํ–ฅํ•ฉ๋‹ˆ๋‹ค. ๋˜ํ•œ, ์„ค๊ณ„ ์ž๋™ํ™” ํ™˜๊ฒฝ์„ ์ง€์†์ ์œผ๋กœ ๊ณ ๋„ํ™”ํ•˜์—ฌ ๋น ๋ฅด๊ณ  ์•ˆ์ •์ ์ธ

SoC ๊ฐœ๋ฐœ์„ ์‹คํ˜„ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

- SoC Design Engineer๋Š” IP ๋ฐ ์„œ๋ธŒ์‹œ์Šคํ…œ ์„ค๊ณ„๋ถ€ํ„ฐ Full Chip ํ†ตํ•ฉ๊นŒ์ง€ SoC ๊ฐœ๋ฐœ ์ „๋ฐ˜์˜ ์—…๋ฌด๋ฅผ

์ˆ˜ํ–‰ํ•ฉ๋‹ˆ๋‹ค. ์‹œ์Šคํ…œ ์•„ํ‚คํ…์ฒ˜ ์„ค๊ณ„์™€ Front-end ์„ค๊ณ„๋ฅผ ๊ธฐ๋ฐ˜์œผ๋กœ ๊ณ ์„ฑ๋Šฅยท๊ณ ํšจ์œจ SoC ๊ตฌํ˜„์„ ๋‹ด๋‹นํ•ฉ๋‹ˆ๋‹ค.


โ–ก ์ฃผ์š” ์—…๋ฌด

- IP/์„œ๋ธŒ์‹œ์Šคํ…œ ์„ค๊ณ„ ๋ฐ Full chip ํ†ตํ•ฉ

- SoC ์•„ํ‚คํ…์ฒ˜ ์„ค๊ณ„

๋ฒ„์Šค ์•„ํ‚คํ…์ฒ˜ ์„ค๊ณ„, ์‹œ์Šคํ…œ ์•„ํ‚คํ…์ฒ˜ ์„ค๊ณ„, ์‹œ์Šคํ…œ ๋ถ„์„

- Full chip SoC ์„ค๊ณ„

Full chip ๋ฐ ์„œ๋ธŒ๋ธ”๋ก ํ†ตํ•ฉ

Power/Reset/Clock controller ์„ค๊ณ„

Full chip ๋ ˆ๋ฒจ ํ”„๋ก ํŠธ์—”๋“œ ์ž‘์—…(Lint, CDC, Synthesis, Formality, STA, SDC ์Šคํฌ๋ฆฝํŠธ ์ž‘์„ฑ ํฌํ•จ)

์„ค๊ณ„์—…๋ฌด ์ž๋™ํ™”(AI ํ™œ์šฉ , Python script)

- IP ๋ฐ ์„œ๋ธŒ์‹œ์Šคํ…œ ์„ค๊ณ„

PCIe, MIPI CSI/DSI, USB, Ethernet๊ณผ ๊ฐ™์€ ๊ณ ์† ์ธํ„ฐํŽ˜์ด์Šค ์„ค๊ณ„

CPU, GPU, NPU, DSP, ISP ๋””๋ฒ„๊ฑฐ, ์ธํ„ฐ๋ŸฝํŠธ ์ปจํŠธ๋กค๋Ÿฌ, MMU, ์บ์‹œ, ๋ฒ„์Šค ์ธํ„ฐ์ปค๋„ฅํŠธ ๋“ฑ ํ”„๋กœ์„ธ์„œ

์„œ๋ธŒ์‹œ์Šคํ…œ ์„ค๊ณ„

Clock controller, Power controller, System monitors, OTP controller์™€ ๊ฐ™์€ ์‹œ์Šคํ…œ IP ์„ค๊ณ„


โ–ก ํ•„์š” ์—ญ๋Ÿ‰

[๊ฒฝ๋ ฅ]

- ์ „์ž๊ณตํ•™, ์ปดํ“จํ„ฐ๊ณตํ•™, ๋ฐ˜๋„์ฒด ๊ด€๋ จ ์ „๊ณต ํ•™์‚ฌ ์ด์ƒ

- ์„ค๊ณ„ ๋ถ„์•ผ๋ฅผ ์ฃผ์š” ์—…๋ฌด๋กœ 2๋…„ ์ด์ƒ์˜ ๊ทผ๋ฌด ๊ฒฝํ—˜์ด ์žˆ์œผ์‹  ๋ถ„

- Verilog ๋˜๋Š” System Verilog๋ฅผ ํ™œ์šฉํ•œ ๊ธฐ๋ณธ RTL ์„ค๊ณ„ ์ง€์‹

- EDA ํˆด ์‚ฌ์šฉ ๊ฒฝํ—˜

- IP/Subsystem/Block ์„ค๊ณ„ ๊ฒฝ๋ ฅ

- ํ•ด์™ธ ์—ฌํ–‰์— ๊ฒฐ๊ฒฉ ์‚ฌ์œ ๊ฐ€ ์—†์œผ์‹  ๋ถ„

[์‹ ์ž…]

- ์ „์ž๊ณตํ•™, ์ปดํ“จํ„ฐ๊ณตํ•™, ๋ฐ˜๋„์ฒด ๊ด€๋ จ ์ „๊ณต ํ•™์‚ฌ ์ด์ƒ

- ์„ค๊ณ„ ๋ถ„์•ผ ๊ด€๋ จ ๊ฒฝ๋ ฅ 2๋…„ ์ดํ•˜

- ๋””์ง€ํ„ธ ํšŒ๋กœ ๋ฐ ๋…ผ๋ฆฌ์„ค๊ณ„ ๊ธฐ๋ณธ ์ง€์‹ ๋ณด์œ 

- ๋ฌธ์ œ ํ•ด๊ฒฐ ๋Šฅ๋ ฅ๊ณผ ๋…ผ๋ฆฌ์  ์‚ฌ๊ณ  ๋Šฅ๋ ฅ

- ์›ํ™œํ•œ ํ˜‘์—… ๋ฐ ์ปค๋ฎค๋‹ˆ์ผ€์ด์…˜ ๋Šฅ๋ ฅ

- ํ•ด์™ธ ์—ฌํ–‰์— ๊ฒฐ๊ฒฉ ์‚ฌ์œ ๊ฐ€ ์—†์œผ์‹  ๋ถ„


โ–ก ์šฐ๋Œ€ ์‚ฌํ•ญ

- ์ž๋™์ฐจ์šฉ ๋ฐ˜๋„์ฒด ์นฉ ์„ค๊ณ„ ๊ฒฝ๋ ฅ

- Full chip ์„ค๊ณ„ ๊ฒฝ๋ ฅ

- C, C++, Python, Tcl ์–ธ์–ด ์‚ฌ์šฉ ๊ฒฝํ—˜

- ๋น„์ฆˆ๋‹ˆ์Šค ์˜์–ด ์˜์‚ฌ์†Œํ†ต ๋Šฅ๋ ฅ์„ ๋ณด์œ ํ•˜์‹  ๋ถ„