RTL/ASIC Design Engineer

Are you passionate about RTL design, automation, and EDA flow development? Join AndGate and become a part of a team building robust and scalable RTL development flows for cutting-edge semiconductor projects.

Experience: 3+ Years

Location: Noida / Bangalore

Notice Period: Immediate to 15 Days Preferred

• Develop, enhance, and maintain RTL design and verification flows.
• Automate RTL development processes using scripting languages such as Python, Perl, or Tcl.
• Integrate EDA tools into seamless design workflows.
• Support RTL designers by improving design productivity and flow efficiency.
• Develop regression, lint, CDC, synthesis, and automation frameworks.
• Debug flow issues and provide timely technical support to design teams.
• Collaborate with RTL, Verification, Physical Design, and CAD teams to optimize development methodologies.
• Maintain flow documentation, user guides, and best practices.

• Strong understanding of RTL design using Verilog/SystemVerilog.
• Hands-on experience with RTL design flows and automation.
• Proficiency in Python, Perl, Tcl, or Shell scripting.
• Knowledge of Linux/Unix environments.
• Experience with Git or other version control systems.
• Familiarity with lint, CDC, synthesis, simulation, and regression flows.
• Good debugging, analytical, and problem-solving skills.
• Excellent communication and collaboration abilities.

• Exposure to ASIC design methodologies.
• Experience with Synopsys, Cadence, or Siemens EDA tools.
• Knowledge of CI/CD or automation pipelines is a plus.

• Work on cutting-edge semiconductor projects.
• Collaborative and learning-focused work environment.
• Opportunity to work with experienced industry professionals.
• Competitive compensation based on your current CTC and client-approved budget.

📩 Interested candidates can share their updated CV via DM or email at: [email protected]

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