Lead Analog Design Engineer

Designation: Lead Analog Design Engineer

Experience: 7–12Years

Reports To: CEO/VP Engineering

Location: Bangalore, India

Job Description:

Join our Analog and Mixed-Signal team to design the high-speed links at the center of our next-

generation SoCs. This is a lead role: you will own the SerDes architecture and its critical circuits, from the first jitter budget through tape-out and lab characterization, and you will set the technical bar for the designers around you. We are looking for someone who wants the whole problem — channel, circuit, layout, and silicon — rather than a slice of it.

What You Will Own:

• Architecture. Define the TX/RX architecture against the channel: analog vs. ADC-based receiver, FFE/CTLE/DFE partitioning, DFE tap count and speculation depth, CDR topology (bang-bang PI- based, baud-rate, or phase-interpolator/injection-locked clocking), and the analog/DSP boundary. Justify each choice with link simulation, not preference.
• Circuit design. Hands-on design of the critical blocks — output driver and terminations, CTLE/VGA, samplers and slicers, summers, clock distribution and phase interpolators, LC/ring VCO and PLL.
• Specification and budgets. Own the jitter budget (RJ/DJ decomposition, BUJ, jitter tolerance/transfer masks), the link budget against compliance channels (e.g. PCIe Gen6, 112G- LR/MR, 800G Ethernet), and the power budget in pJ/bit.
• Physical realization. Drive floorplan, shielding, supply and reference distribution, and parasitic- aware closure with the layout team; own post-layout, EM/IR, and Monte Carlo sign-off across PVT.
• Silicon. Lead bring-up and characterization — BER bathtub and eye-margin measurement, jitter decomposition, jitter tolerance sweeps, adaptation-loop debug — and close the loop back into the next revision.

What We Require:

• 7+ years of high-speed SerDes circuit design in production silicon (BE/BTech/MS/PhD in EE or equivalent). We care about depth in high-speed links, not total years in analog.
• At least one SerDes tape-out at ≥32 Gbps where you owned a critical block through characterization; be ready to discuss first-silicon learnings.
• Transistor-level command of at least two of: TX drivers and impedance/termination control; CTLE/VGA and analog front end; DFE/FFE implementation including speculative/unrolled first taps; samplers and offset correction; CDR loops and phase interpolators; high-speed clock distribution.
• Clocking and jitter fluency: LC/ring VCO design, PLL loop dynamics, phase-noise-to-jitter conversion, and the ability to build and defend a jitter budget.
• Link-level modelling: S-parameter/channel modelling, statistical eye and BER analysis (StatEye/IBIS-AMI class flows), and proving circuit decisions at the link level before silicon.

Educational Qualifications:

• BTech/MS/ PhD with 7+ years of industry experience in analog mixed-signal design, particularly in high-speed circuits.
• Hands-on design experience with multi-Gbps SERDES and high-speed serial interfaces (e.g., PCIe, USB, Ethernet), including TX/RX architectures, clocking, and equalization techniques.
• Strong fundamentals in mixed-signal circuit architecture and design for SERDES transmitters, receivers, and PLL/DLL/clocking, with a solid understanding of signal integrity optimization, noise reduction techniques, and multi-GHz low-jitter clock generation and distribution.
• Proven track record with direct silicon tape-out of the above-mentioned blocks.
• Experience in using development tools including Cadence Virtuoso, AFS, Siemens, MATLAB and Verilog modeling.
• Experience in post-silicon validation, including hands-on use of lab equipment, debugging, and characterization of analog mixed-signal circuits.