Senior Analog Design Engineer

Company Description Chiplogic Technologies (Chiplogic) is an IP and Product Engineering Services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML domains. The company delivers high-quality, dependable services, including Offshore Development Centers (ODC) and full turnkey semiconductor design from concept to silicon. Chiplogic also provides system solutions, proofs of concept (POCs), and IoT deployments, with a strong focus on end-to-end delivery. Its AI/ML offerings are built around the proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, enabling innovative video and real-time analytics solutions.

Role Description This is a full-time, on-site Senior Analog Design Engineer role based in Bengaluru. The role involves designing, simulating, and verifying analog circuits and subsystems for semiconductor products, with a focus on robust performance, power efficiency, and manufacturability. Responsibilities include developing power management solutions, collaborating with digital and layout teams, reviewing schematics and layout, and performing corner, Monte Carlo, and reliability analyses. The engineer will create and maintain design documentation, participate in design reviews, support silicon bring-up and validation, and contribute to continuous improvement of design methodologies and best practices.

• Strong experience in Analog IC Design and Power Management ICs (PMIC) .
• Hands-on experience with High Voltage (HV) CMOS/BCD technologies .
• Design experience with:
• High Side Gate Drivers
• Charge Pumps
• Level Shifters
• LDOs
• Bandgap References
• Current Mirrors
• Comparators
• Expertise in transistor-level circuit design and optimization.
• Strong understanding of:
• High Voltage MOS devices
• Device reliability
• ESD concepts
• Latch-up considerations
• Experience with:
• PVT analysis
• Monte Carlo simulations
• Corner analysis
• Worst-case verification
• Hands-on experience with Cadence Virtuoso , Spectre , ADE Explorer/Assembler, and LVS/DRC verification flows.
• Experience in post-layout extraction (PEX) simulations.
• Good understanding of layout-dependent effects and matching techniques.

• The experience should be 8+ years not less then this.
• Experience in Automotive IC Design (AEC-Q100) .
• Knowledge of functional safety concepts (ISO 26262) is an advantage.
• Familiarity with BCD/High Voltage process technologies.
• Experience with silicon bring-up and lab validation.
• Strong debugging and problem-solving skills.
• Excellent communication and cross-functional collaboration abilities.