FPGA Design Engineer — Medical & Video Systems

About Us

HTIC - IIT Madras is focused on developing advanced medical imaging and real-time video

processing systems for endoscopy and other clinical applications. Our team combines FPGA

hardware design, embedded software, and image signal processing to deliver low-latency,

clinically robust products.

Role Overview

We are hiring an FPGA Design Engineer with 2–3 years of experience to design and

implement FPGA/SoC modules for production-grade imaging/video pipelines. You will work

on RTL design, video/ISP/DSP pipeline integration, and PS/PL firmware, collaborating

closely with algorithm and system teams.

Key Responsibilities

• Design, implement, verify, and optimise RTL modules in VHDL/Verilog for Zynq/Zynq UltraScale+ platforms.
• Develop and integrate video/data pipelines (AXI-Stream, AXI4, DMA) and ISP/DSP blocks (color conversion, filtering, scaling, denoising).
• Use Xilinx Vivado for synthesis, implementation, timing closure, and bitstream generation.
• Develop PS/PL firmware and system software using Vitis and Petalinux (boot flow, device tree, drivers).
• Map algorithms to hardware (HLS familiarity helpful) and collaborate with IITM faculty guides and internal teams on aligned project work.
• Perform simulation, FPGA bring-up, and system verification; debug using ILA, JTAG, logic analyzers, and profiling tools.
• Optimise designs for latency, resource use, and power; follow medical product documentation and research reporting practices.
• Contribute to lab testing, manufacturing validation, and field support.

Required Qualifications and Skills

• 2–3 years professional experience in FPGA/SoC design.
• Strong RTL coding in VHDL or Verilog; solid synchronous digital design skills.
• Practical experience with Xilinx Vivado flow and timing closure.
• Experience with Vitis and Petalinux (cross-builds, device tree, kernel modules).
• Knowledge of video/ISP/DSP concepts and AXI protocols.
• Familiarity with DDR memory interfaces, DMA integration, and debugging tools (ModelSim/XSIM, ILA).
• Comfortable in Linux environments and scripting (Python/Bash).
• Bachelor’s/Master’s degree in Electronics, ECE, or related discipline.

Good to have

• HLS (C/C++ to RTL) experience, Vitis Vision familiarity.
• HDMI/SDI or GTH transceiver experience and knowledge of video standards.
• Prior exposure to medical device development or regulated quality systems.
• Interest in research, publications, and academic collaboration.

How to Apply

• Send your CV to : [email protected]