Digital Design Verification Engineer
📌Bengaluru, India 🇮🇳
⏱︎ full-time
🧙♂️ senior
- Develop and execute comprehensive verification plans based on design specifications and architecture documents.
- Build scalable and reusable test environments using System Verilog and UVM.
- Write directed and constrained-random test cases to validate functionality, performance, and corner cases.
- Perform functional coverage analysis and drive coverage closure.
- Debug test failures, file bugs, and work with RTL designers to resolve issues.
- Maintain and run regression suites to ensure design stability and quality.
- Participate in code reviews, documentation, and process :
- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related discipline.
- 5 + years of experience in digital design verification.
- Strong knowledge of System Verilog and UVM methodology.
- Experience with industry-standard simulators (VCS, Xcelium, Questa) and waveform viewers (Verdi, DVE, Sim Vision).
- Good understanding of digital design concepts including FSMs, pipelines, memories, and buses (AXI, AHB, APB).
-
Familiarity with scripting languages (Python, Perl, Tcl, Shell) for automation.
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Employment
⏱︎ full-time
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Experience
🧙♂️ senior
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Skills
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Industry
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