Design Verification Engineer
Radiant ↗
📍 Bengaluru, India 🇮🇳
full-time
mid-level
Expired
Posted —
This job posting has expired
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Key Skills
EthernetSystemVerilogUVMVerificationDebugging
Industry
SemiconductorTelecommunications
Job Description
We are looking for a Design Verification (DV) Engineer with strong expertise in Ethernet protocols to join our verification team. The candidate will be responsible for verifying complex networking IPs (MAC/PCS/PHY) and ensuring high-quality silicon delivery.
Responsibilities
Responsibilities
- Develop and execute verification plans for Ethernet IPs.
- Build and maintain UVM/SystemVerilog-based benches.
- Create cases, sequences, scoreboards, and coverage models.
- Debug RTL issues and analyse failures using simulation tools.
- Work closely with design, architecture, and physical design teams.
- Ensure functional and code coverage closure.
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Participate in review cycles (test plan, code, coverage).
- Strong hands-on experience in SystemVerilog and UVM.
- Good understanding of Ethernet protocols (1G / 10G / 25G / 40G / 100G).
- Knowledge of MAC, PCS, and PHY layers.
- Experience in verification methodologies (UVM, OVM/VMM).
- Debugging skills using tools like Verdi / SimVision / DVE.
- Experience with coverage-driven verification.
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Familiarity with protocol compliance and packet-level debugging.
- Experience with AXI / AHB / APB interfaces.
- Knowledge of SerDes / high-speed interfaces.
- Scripting knowledge in Python / Perl / Shell.
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Exposure to emulation / FPGA prototyping.
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Key Skills
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