Design Verification Engineer
Creeno Solutions Pvt Ltd ↗
📍 Bengaluru, India 🇮🇳
full-time
mid-level
Expired
Posted —
This job posting has expired
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Key Skills
EthernetSystemVerilogUVMASICSoC
Industry
SemiconductorTelecommunications
Job Description
Key Responsibilities
- Develop verification plans based on Ethernet protocol specifications (e.g., IEEE 802.3).
- Design and implement constrained-random and directed test benches using System Verilog and UVM.
- Execute test plans and run regressions to verify Ethernet MAC/PHY functionality and compliance.
- Work closely with design, architecture, and validation teams to identify corner cases and root-cause failures.
- Integrate third-party Ethernet IPs and validate in SoC environment.
- Perform coverage analysis and drive closure on functional and code coverage.
- Debug test failures using waveform viewers and simulation logs.
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Collaborate with post-silicon and validation teams to support bring-up and debug.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 5-10 years of experience in ASIC/SoC design verification, with specific focus on Ethernet protocol (10/25/40/100/400G).
- Hands-on experience with System Verilog and UVM.
- Good understanding of Ethernet protocol layers: MAC, PCS, PMA, and PHY.
- Strong debugging skills with tools such as Verdi, DVE, or Sim Vision.
- Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence xcelium).
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Familiarity with scripting languages (Python, Perl, or Shell) for automation.
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Key Skills
EthernetSystemVerilogUVMASICSoC
Industry
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