Design Verification Engineer

We are expanding our verification team and looking for experienced Design Verification Engineers who are passionate about building robust and high-quality semiconductor solutions.

Role: Design Verification Engineer

Experience: 4–10 years

Location: Bangalore (On-site, Full-time)

Joining: Immediate to 15 days

Key Requirements

• Strong hands-on experience in SystemVerilog and UVM (SV-UVM)

• Solid expertise in protocol-based verification

• Proven experience in SoC-level verification or deep, hands-on expertise in one or more protocols

• Strong debugging and problem-solving skills

• Experience working in full verification lifecycle

Preferred Skills

• Hands-on experience with PCIe protocol

• Exposure to high-speed interface verification is a plus

What You’ll Work On

• Developing and executing verification plans for complex SoCs

• Building reusable verification environments using SV-UVM

• Protocol-level verification and debugging

• Collaborating closely with design and architecture teams

If you’re someone who enjoys deep technical work and hands-on verification challenges, we’d love to hear from you.