Design Verification Engineer

Job Role : Verification Engineer

Location : Bangalore (F2F interview)

Exp : 1 to 10 years

Key skills:

• SoC, SV,UVM, Assertions. AMBA protocols Must.
• 1 Scripting experience Python/Perl/TCL/Shell must.
• C langugae is must.
• Security IP DV , GLS & UPF exp is desriable.

Requirements:

• B.E/B.Tech/M.Tech in ECE/EE/CS or equivalent with 3–5 years of relevant experience.
• Strong fundamentals in digital design and memory systems, particularly on‑chip SRAM behavior and initialization requirements.
• Experience validating reset, clock, and power interactions, including low‑power and clock‑gating scenarios.
• Solid understanding of SoC integration concepts: memory controllers, interconnect/NoC behavior (e.g., AXI), and visibility during bring‑up.
• Hands‑on pre‑silicon validation experience: test planning, stimulus creation, debug, and coverage closure.
• JTAG fundamentals: register access, run‑control, basic scripting for bring‑up and debug. Strong debugging skills using traces, and logs to isolate functional and sequencing issues.
• Scripting in Python/Perl/TCL/Shell for automation, log parsing, and regression workflows. Ability to reason from first principles and design corner‑case and stress scenarios for early‑boot and memory setup logic.