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NVIDIA

ASIC Verification Engineer

๐Ÿ“ŒShanghai, China ๐Ÿ‡จ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ mid-level

NVIDIA MMPLEX team delivers cutting-edge IP solutions to multiple NVIDIA product lines, for example: GeForce, automotive etc. We are looking to grow our teams with the smartest people in the world, join us if you want to learn about worldโ€™s leading IP technology and development process.

What You'll Be Doing

  • Reading design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
  • B uilding block/IP testbench based on UVM methodology.
  • Building test cases and regression flow. Triage failures in regression and help designer root cause the bug.
  • Measuring various metrics (passing rate, functional coverage, etc.) and monitor its health.
  • Analyzing functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
  • Developing necessary tools to improve team's efficiency.

What We Need To See

  • BS / MS in electrical / computer engineering and related.
  • 3+ years (MS) or 5+ years (BS) working experience.
  • Proficient in using simulator and related tools such as VCS, Verdi, Xcelium, etc..
  • Structural thoughts on verification planning in extracting requirements and organizing stimulus legality.
  • Deep understanding in System Verilog, especially in writing complex random constraints and coverage model.
  • Deep understanding in UVM including phase running, factory overriding, message reporting, etc..
  • Fully experienced building testbench from scratch as well as BFM modeling.
  • Familiar with python programing.
  • Good communication skills in English.

JR1997811

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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ mid-level

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