ASIC Solution Architect Engineer

Company:

Job Area:

Engineering Group, Engineering Group > Hardware Applications Engineering

General Summary:

Job Overview

We are seeking an experienced Senior ASIC Solution Architect to lead customer technical engagements and drive solution definition for next-generation Data Center ASIC projects.

This role serves as the technical owner for solution definition, architecture planning, and technology selection activities throughout the early phases of customer engagements and program development.

You will work closely with hyperscalers, cloud service providers, AI infrastructure companies, and strategic ASIC customers to translate business and system requirements into scalable end-to-end ASIC solutions leveraging Qualcomm technologies, IP portfolio, and platform capabilities. Will Acts as technical owner for solution definition activities.

The successful candidate will act as a trusted technical advisor, helping customers define optimal architectures, evaluate technology tradeoffs, identify architecture and technology risks early, and accelerate successful deployment of custom silicon solutions.

Key Responsibilities

1. Engage with strategic customers to understand business objectives, system requirements, and technical challenges; translate customer requirements into ASIC implementation strategies and solution roadmaps. Act as the technical owner for requirement analysis, solution definition, and architecture recommendations during customer engagements.

2. Lead architecture feasibility studies and technical tradeoff analysis covering performance, power, area, cost, schedule, scalability, and technology selection.

3. Define and recommend optimal ASIC platform and subsystem architectures involving HBM, PCIe, CXL, UCIe, SerDes, Ethernet, Network-on-Chip (NoC), Chipset architectures, and memory subsystems.

4. Guide customers on Qualcomm IP selection, integration strategies, system partitioning, and technology adoption to maximize solution value and project success.

5. Serve as the technical lead during pre-sales engagements and early program definition phases; lead customer technical reviews, architecture workshops, and solution discussions.

6. Coordinate cross-functional activities across Product Management, Design Engineering, Verification, Physical Design, Program Management, Customer Engineering, and ecosystem partners, etc.

7. Identify architecture and implementation risks during project planning, including performance targets, power budgets, memory bandwidth requirements, chipset partitioning strategies, technology node selection, and integration challenges.

8. Develop mitigation plans and architectural recommendations to address technical risks before implementation begins.

9. Establish reusable customer solution methodologies, including architecture review processes, design review checklists, solution playbooks, technical best practices, and reference architectures.

10. Deliver technical workshops, customer training sessions, executive briefings, and technology presentations to support customer success and solution adoption.

11. Build long-term trusted relationships with customer engineering and architecture teams and serve as a strategic technology advisor for key accounts.

12. Collect customer feedback on future technology requirements and coordinate with internal engineering and product teams to drive technology roadmap planning and continuous improvement.

Required Qualifications

1. Bachelor’s degree or above in Microelectronics, Electrical Engineering, Integrated Circuit Design, Computer Engineering, or related majors.

2. More than 12 years of semiconductor industry experience with solid background in ASIC/SoC architecture, development, or customer technical engagement.

3. Minimum 6 years of experience in ASIC or SoC architecture, system design, solution development, customer engineering, or related technical leadership roles.

4. Strong understanding of the complete ASIC development lifecycle including architecture definition, RTL design, verification, physical implementation, signoff, tapeout, and silicon bring-up.

5. Deep knowledge of Data Center ASIC technologies including one or more of the following domains: HBM/PCIe/CXL/UCIe/SerDes/Ethernet/Chipset Architectures/AI Accelerators/Networking ASICs

6. Strong understanding of advanced semiconductor process technologies and ASIC implementation challenges.

7. Proven ability to lead architecture reviews, technical planning activities, and cross-functional engineering discussions.

8. Proven ability to define creative and scalable architecture solutions for complex ASIC and SoC designs through system-level tradeoff analysis and technical innovation.

9. Proven track record of successfully guiding design, verification, and implementation teams from architecture definition through tapeout and silicon bring-up of complex ASIC products.

10. Excellent customer-facing communication skills and ability to effectively engage with engineers, architects, executives, and business stakeholders.

11. Fluent oral and written English for regular communication with global customers, ecosystem partners, and engineering teams.

12. Strong analytical thinking, problem-solving abilities, and capability to drive complex technical decisions under ambiguity.

Preferred Qualifications

1. Experience supporting hyperscaler, cloud infrastructure, AI accelerator, networking, HPC, DPU, or XPU programs.

2. Experience working in semiconductor Fabless, IP suppliers, top design service companies.

3. Demonstrated experience in customer-facing roles such as: Solution Architect, System Architect, ASIC Architect, Application Engineer, Technical Marketing Engineer.

4. Experience supporting advanced-node ASIC projects including 7nm, 5nm, or beyond.

5. Familiarity with Qualcomm technologies, ecosystem partners, IP business models.

6. Experience developing customer enablement programs, technical training content, design guidelines, and solution methodologies.

7. Familiarity with Python, Tcl, or system-level modeling tools for design analysis and solution evaluation.

Minimum Qualifications:

• Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 6+ years of Hardware Applications Engineering or Hardware Design experience or related work experience.
OR
Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field and 5+ years of Hardware Applications Engineering or Hardware Design experience or related work experience.
OR
PhD in Electrical/Electronics Engineering, Computer Engineering, or related field and 4+ years of Hardware Applications Engineering or Hardware Design experience or related work experience.

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