ASIC Engineer - New College Grad 2026
📌Shanghai, China 🇨🇳
⏱︎ full-time
🧙♂️ entry-level
What You’ll Be Doing
- Micro architecture design.
- RTL (Verilog) coding.
- Design implementation using Synopsys/Cadence tools.
- Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction)
- Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off. (PD Direction)
- Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction)
- FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction)
-
Methodology in any of above areas.
- MS degree from EE/CS or related majors from a prestigious university.
- Good knowledge in digital circuit design.
- Experience in using Verilog HDL.
- Experience in various of ASIC EDA tools.
- Fluent in English reading and writing.
-
Self-motivated, good team player.
- Proven ability to work independently as well as in a multi-disciplinary group environment
- Good command of C/C++ programming language.
-
Hand-on experience in any related area is a plus.
Senior Embedded Software Engineer
@ Embedd 
What we're looking for
At embedd.it, we power hardware-software integration in embedded devices. We turn fragmented semiconductor chip data into configurable digital twins, then deterministically generate code, tests, and documentation – making integration faster, cheaper, and resilient to supply chain shocks.
We’re looking for a true legend – someone with abstract thinking and deep expertise in low-level software development. You’ll build vendor-agnostic tooling for MCU and peripheral integration to solve hardware-software integration once and for all. We work at the intersection of embedded systems, code generation, compilers, and machine learning. It’s your chance to help redefine how low-level development is done.
Responsibilities
- Drive the architecture of the driver structures and system layout
- Define scalable patterns for cross-architectural integration across bare-metal, Zephyr, Linux, and other environments
- Deconstruct complex SoC device trees and translate hardware descriptions into structured internal models for automated reasoning
- Partner with the ML team to shape data and annotation models for AI-driven data-extraction tooling
Qualifications
- 5+ years of experience in embedded systems development, including bare-metal and RTOS-based systems
- Proficiency in C/C++
- Familiarity with firmware configuration, SoC bring-up, and system-level debugging
- Hands-on experience with code generation tools, or low-level compiler/decompiler/emulator technologies
- Strong background in embedded toolchains: compilers, linkers, debuggers, and build systems
- Python or scripting for automation and tooling is a plus
- Experience with functional-safety standards is a plus
Why embedd.it?
- Dynamic, venture-backed team of engineers challenging the status quo 🚀
- Work at the intersection of embedded systems, code generators, compilers, and ML 🤖
- Unusual challenges requiring out-of-the-box abstract thinking 🧠
- Competitive compensation: cash + equity 💰
- Remote work possible 🌍
About Us
embedd.it is a UK-based startup reinventing embedded development. Our platform transforms unstructured semiconductor data into structured digital twins, enabling automatic generation of drivers, tests, and documentation. We're building a single, traceable source of truth to make integration fast, vendor-agnostic, and future-proof.
Other similar jobs
Senior ASIC Timing Engineer
@ NVIDIA, 📍China 🇨🇳
Senior ASIC Timing Engineer
@ NVIDIA, 📍China 🇨🇳
CPU Physical Design Principal Engineer
@ Qualcomm, 📍China 🇨🇳
ASIC Analog Design Engineer - REF79515L
@ Continental, 📍China 🇨🇳
Staff Engineer, Digital IC Design
@ Marvell Technology, 📍China 🇨🇳
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC Physical Design Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
-
Employment
⏱︎ full-time
-
Experience
🧙♂️ entry-level
-
Skills
-
Industry
-
Find similar jobs
Senior ASIC Timing Engineer
@ NVIDIA, 📍China 🇨🇳
Senior ASIC Timing Engineer
@ NVIDIA, 📍China 🇨🇳
CPU Physical Design Principal Engineer
@ Qualcomm, 📍China 🇨🇳
ASIC Analog Design Engineer - REF79515L
@ Continental, 📍China 🇨🇳
Staff Engineer, Digital IC Design
@ Marvell Technology, 📍China 🇨🇳
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC Physical Design Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍China 🇨🇳