Responsibilities:
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Work on SOC Front-end design team, be responsible for the SOC subsystem design, including subsystem integration, RTL coding, design rule check and constrain delivery.
Requirements
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Strong Verilog and C coding skills
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Knowledge of on-chip bus protocols: AMBA, AXI or similar is a plus
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Extensive knowledge and experience in front-end implementation tasks such as constraint definition (timing & power), synthesis, power analysis, equivalence checking and STA is a plus
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Good English communication skills.
More information about NXP in Greater China...