Technical Lead - FPGA Design Engineer

Job Summary:

We seek a Technical FPGA Lead with 7-10 years of experience to architect and deliver high-speed FPGA designs. You'll lead a small team, drive micro-level architecture for performance-critical systems and ensure seamless integration of protocols like PCIe, MIPI, and 10G Ethernet. If you thrive on lab debugging and optimizing complex designs, this is your role.

Key Responsibilities:

• Define and document micro-level architectures for high-speed data paths, ensuring optimal resource utilization and low latency performance.
• Lead end-to-end FPGA design cycles, from RTL development to implementation and verification on Xilinx (Kintex/Versal) and Altera platforms.
• Execute rigorous Static Timing Analysis (STA) and resolve complex constraints. Analyze and mitigate Clock Domain Crossing (CDC) issues to ensure design robustness.
• Implement and validate protocols like PCIe, MIPI, DDR, USB and 10G Ethernet using RTL (Verilog/VHDL).
• design debugging with lab equipment like oscilloscopes, logic analyzers, ILA, and SignalTap.
• Mentor junior engineers, conduct code reviews, and collaborate with cross-functional teams (Hardware and software).

Required Qualifications:

• Bachelor's/Master's in Electrical Engineering, Computer Engineering, or related field.
• 7-10 years of hands-on experience with diverse FPGAs (Xilinx and Altera/Intel).
• Expert in RTL design, STA, and CDC; proven track record in high-speed design (>10Gbps).
• Deep experience with PCIe, MIPI protocols, and 10G Ethernet (At Least with one protocol).
• Proficiency using lab tools: oscilloscopes, logic analyzers, ILA/SignalTap.
• Strong leadership skills with experience managing small teams in agile environments.
• Familiarity with Vivado, Quartus, and scripting (TCL/Python) is a plus.
• Familiarity with Gigabit transceiver with NRZ and PAM4 is a plus
• Willingness to learn new architectures and protocols as technology evolves.

Additional Requirement:

• Immediate joiners or candidates who can join within 30 days are preferred.