SoC Physical Design Engineer, PnR

Summary

We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance u0026 low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle.

Description

• You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.n- You will also collaborate to drive methodologies and
  
  

Minimum Qualifications

Minimum BS and 3+ years of relevant industry experience

Preferred Qualifications

Knowledgeable in partition level Pu0026R implementation including floorplanning, clock u0026 power distribution, timing closure, and physical u0026 electrical verification.nKnowledge of PD construction u0026 analysis flows and methodology.nStrong interpersonal skills.nRecent successful tapeouts in deep submicron technology.nExperience with large SOC designs (u003e20M gates) with frequencies in excess of 1GHZ.nShown ability to execute to stringent schedule u0026 die size requirements.nExperienced in industry standard tools and understanding their capabilities and underlying algorithms.

Pay & Benefits

u003cpu003eApple accepts applications to this posting on an ongoing basis.u003c/pu003e