Senior RTL Engineer

Key Responsibilities:

Clock & Reset: Architect complex multi-domain clock trees, gated

clocks, and glitch-free mux structures with async reset deassertion.

CDC: Own full CDC closure — define synchronizer libraries, close

structural CDC, author waivers, and lead sign-off via

Spyglass/Questa/Jasper Gold.

Linting & Quality: Drive block and top-level lint sign-off; define

team coding guidelines and enforce zero-critical-waiver policy.

Memory Integration: Architect memory subsystems with

SP/DP/CAM macros; own BIST, ECC, redundancy logic,

and STA constraint delivery.

RTL Integration: Lead subsystem and SoC-level RTL

integration; resolve interface protocol conflicts and own

pre-synthesis sign-off checklists.

RTL Development: Develop and review high performance

synthesizable System Verilog; mentor junior

engineers on RTL best practices.

Required Qualifications:

B.E./B. Tech/M. Tech in Electronics, VLSI, or related field.

▸ 7-8 years of RTL design experience in ASIC/SoC

environments.

▸ Deep expertise in System Verilog/Verilog, CDC closure, and

lint sign-off.

▸ Proven ownership of memory subsystem integration and STA

constraint delivery.

▸ Strong working knowledge of synthesis (DC/Genus), STA, and

timing closure flows.

▸ Experience leading RTL integration at subsystem or chip level

Nice to Have:

Architecture and microarchitecture spec authoring

experience.

Hands-on with high-speed interfaces: SerDes, PCIe

Gen4/5, DDR5, or HBM.

▸ Formal verification (Jasper Gold/VC Formal) for CDC and

property checking.

▸ UVM testbench co-development and coverage closure

ownership.

▸ Python/Tcl EDA scripting; tape-out at 5nm or below.

Tools & Technologies:

Spyglass

System Verilog

Questa CDC

Jasper Gold

AXI4 / APB

Design Compiler

VCS

Memory Compilers

Python / Tcl

Git / Perforce

Genus / DC

UVM / SVA

VC Formal

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